A
Andrew Holme
Guest
I'm a bit confused by a couple of things on the AD9901 datasheet:
Rev. A - http://www.sss-mag.com/pdf/ad9901.pdf
Rev. B -
http://www.analog.com/UploadedFiles/Data_Sheets/36342005AD9901_b.pdf
Firstly, in the functional block diagram in revision B, the logic symbol
used for the exclusive-OR gate appears to have a blob on the output - making
it an exclusive-NOR; however, I think it should be a plain XOR - as it was
in revision A. On page 6, it says: "Near lock, the frequency discriminator
flip-flops provide *constant* HIGH levels to gate the XOR output to the
final output."
Also, aren't the captions the wrong way around on rev A figs 3 and 4, and
rev B figs 5 and 6? Surely, the output duty-cycle exceeds 50% when phi-out
(VCO) lags?
Can someone put me right on the above?
TIA
Andrew.
Rev. A - http://www.sss-mag.com/pdf/ad9901.pdf
Rev. B -
http://www.analog.com/UploadedFiles/Data_Sheets/36342005AD9901_b.pdf
Firstly, in the functional block diagram in revision B, the logic symbol
used for the exclusive-OR gate appears to have a blob on the output - making
it an exclusive-NOR; however, I think it should be a plain XOR - as it was
in revision A. On page 6, it says: "Near lock, the frequency discriminator
flip-flops provide *constant* HIGH levels to gate the XOR output to the
final output."
Also, aren't the captions the wrong way around on rev A figs 3 and 4, and
rev B figs 5 and 6? Surely, the output duty-cycle exceeds 50% when phi-out
(VCO) lags?
Can someone put me right on the above?
TIA
Andrew.