Synthesisable fixed-point arithmetic package

J

Jonathan Bromley

Guest
Six months after I said "it's nearly done", I've now finished an
alpha-test version of the synthesisable VHDL fixed-point package
I promised. Doesn't time fly when you're enjoying yourself? :)

I've published it on our corporate website but, as yet, there are
no links to it from elsewhere on the site. So you need to go
straight to it using this link:

http://www.doulos.co.uk/knowhow/vhdl_models/fp_arith/

At present, all you get is a VHDL package and package body,
and a PDF doc describing it.

Any feedback is welcome. Please note that it is very much
in an experimental state at present. It is in desperate need
of example designs and a validation test suite; contributions
towards either will be gratefully received, and acknowledged in
future releases.

I would be especially grateful for any indication of whether it's
aiming in the right direction, and how it could be enhanced or
made more useful.

My employers are not responsible for any part of the package.
Any comments on it should come directly to me at the
address given below.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
You may also be interested to know that there is both a fixed point
and floating point package being developed under IEEE 1076.3.

You can find out more information at:

1076.3 General: http://www.vhdl.org/vhdlsynth/
Floating Point: http://www.eda.org/fphdl/
Fixed Point: http://www.vhdl.org/vhdlsynth/proposals/dave_p3.html

Cheers,
Jim Lewis
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:Jim@SynthWorks.com
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jonathan Bromley wrote:
Six months after I said "it's nearly done", I've now finished an
alpha-test version of the synthesisable VHDL fixed-point package
I promised. Doesn't time fly when you're enjoying yourself? :)

I've published it on our corporate website but, as yet, there are
no links to it from elsewhere on the site. So you need to go
straight to it using this link:

http://www.doulos.co.uk/knowhow/vhdl_models/fp_arith/

At present, all you get is a VHDL package and package body,
and a PDF doc describing it.

Any feedback is welcome. Please note that it is very much
in an experimental state at present. It is in desperate need
of example designs and a validation test suite; contributions
towards either will be gratefully received, and acknowledged in
future releases.

I would be especially grateful for any indication of whether it's
aiming in the right direction, and how it could be enhanced or
made more useful.

My employers are not responsible for any part of the package.
Any comments on it should come directly to me at the
address given below.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Click to expand...
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top