Synchronization between CPU-clock and FPGA clock.

[One Day & A Knight]

Hi,

I want to know how to properly interface between the CPU clock and the FPGA
clock.
My board has separate clocks for CPU and FPGA.

Best Regards,
Kelvin

 

[Vinh Pham]

Heya Kelvin,

I want to know how to properly interface between the CPU clock and the
FPGA
clock.

That's a pretty broad question. There are all sorts of solutions that vary
in complexity. It will help if you can explain your design situation in
more detail. What sort of data is flowing between the two clock domains?
What's the interaction like?

Regards,
Vinh

 

[One Day & A Knight]

The CPU will write bytes into a register, at 8M-bytes/second...
The FPGA will read that register and do some signal processing (Shifting,
addition, etc) on it.
Can FPGA use the same clock with the CPU?

CPU is a ARM7...FPGA is Spartan-2, 250K...





Vinh Pham <a@a.a> wrote in message
news:xHCzb.3169$WT6.719@twister.socal.rr.com...

Heya Kelvin,

I want to know how to properly interface between the CPU clock and the
FPGA
clock.

That's a pretty broad question. There are all sorts of solutions that
vary
in complexity. It will help if you can explain your design situation in
more detail. What sort of data is flowing between the two clock domains?
What's the interaction like?

Regards,
Vinh

 

[Mike Treseler]

One Day & A Knight wrote:

Hi,

I want to know how to properly interface between the CPU clock and the FPGA
clock.
My board has separate clocks for CPU and FPGA.

Make a ready with a fpga register and synch it to cpu_clk.
Make an ack bit with a cpu port and synch it to fpga_clk.

Why not run the fpga on the cpu clk?

-- Mike Treseler

 

[Vinh Pham]

Google's a great tool for digging up information, and it can be used to
search news groups exclusively.

Go to groups.google.com (instead of www.google.com) and punch in:

crossing clock boundaries group:comp.arch.fpga

It'll bring up past conversations where people have already rehashed this
same issue. You'll get the information you need much faster that way. But
here's one possible solution:


The key thing to synchronizing is making sure the data doesn't change during
the clock edge where it's being paid attention to (i.e. you want to
guarantee that you don't have a hold/setup-time violation).

Yeah the easiest thing to do is to avoid the problem by using the CPU clock
(or perhaps more accurately the CPU bus clock), unless it happens to be too
slow for your FPGA to achieve the performance you need. But if your
algorithm can be executed in parallel, you can increase performance without
increasing your clock speed. Or you could use the clock doubling feature of
the DLLs, which should maintain a constant relationship between the clock
edges, though I have no experience with this.

If for some reason you can't have the same clock, then having your FPGA
clock be faster than the CPU clock will make things easier. One straight
forward method is for the CPU to write it's data to one register. Then
write a 0 and then a 1 to another register. The output of this single bit
register is sent serially through two flip flops that are clocked on the
FPGA clock. You then send it through one more flip flop and logic that
detects when the input of this flip flop is 1 and the output is 0. This is
a simple edge detect circuit that will generate a clock enable that will
tell a register to latch the data from the CPU data register.

Basically you have a system that tells the FPGA when the CPU data is stable
and safe to read.

With a bit more work on the hardware side, you can eliminate the CPU having
to write a 0 and a 1 by creating logic that detects when the CPU does a
write to the data register.

This is a low bandwidth solution. If you need more bandwidth (which it
doesn't sound like you do), then you can look into implementing an
asynchronous fifo. And you'll have to do something slightly different if
your FPGA clock has to be slower than the CPU clock, for some reason.

Good luck on your project.


Regards,
Vinh