P
Paul Baxter
Guest
In VHDL I'm forever writing process statements to produce
1) a simple clocked FF
2) As above with async reset
3) As above with clock enable
I must write things like
process (clk, reset)
begin
if (reset = '1') then
signal <= '0';
elsif (rising_edge(clk)) then
if (enable = '1') then
signal <= next_signal_value;
end if;
end if;
end process;
At the risk of looking stupid, surely there is a simpler way.
signal <= next_signal_value when (rising_edge(clk)); -- ??
Paul
1) a simple clocked FF
2) As above with async reset
3) As above with clock enable
I must write things like
process (clk, reset)
begin
if (reset = '1') then
signal <= '0';
elsif (rising_edge(clk)) then
if (enable = '1') then
signal <= next_signal_value;
end if;
end if;
end process;
At the risk of looking stupid, surely there is a simpler way.
signal <= next_signal_value when (rising_edge(clk)); -- ??
Paul