M
Mike
Guest
Hi
I declared a std_logic_vector(7 downto 0) type port
in my VHDL program. In the testbench, I will try
to assign some value to this port. But after synthesis
using Synopsys Design Compiler, I found this port can't
accept the value from signal assignment in the test bench
and the value of this port becomes "XX".
BTW, even I initialize this port to "ZZZZZZZZ"
in the entity definition, it still doesn't work.
Could anyone give me some adivce about this problem.
Thanks a lot.
Mike
I declared a std_logic_vector(7 downto 0) type port
in my VHDL program. In the testbench, I will try
to assign some value to this port. But after synthesis
using Synopsys Design Compiler, I found this port can't
accept the value from signal assignment in the test bench
and the value of this port becomes "XX".
BTW, even I initialize this port to "ZZZZZZZZ"
in the entity definition, it still doesn't work.
Could anyone give me some adivce about this problem.
Thanks a lot.
Mike