B
Brad Smallridge
Guest
Hello comp.lang.vhdl,
I am designing a specialized SDRAM controller and have a question about the
best way to set up some timing signals. I generally have a good idea about
what signals have to issued at certain clock times. I set up a rather long
clock cycle, separating the sync from the combo logic like this:
p1: process (fastclk3)
begin
if (fastclk3'event and fastclk3 = '1') then
fastclkcnt <= fastclkcntnext;
mras <= mrasnext;
.... and so on
p2: process (fastclkcnt)
begin
if ( fastclkcnt = 50 ) then
fastclkcntnext <= "011110"; --30
else
fastclkcntnext <= fastclkcnt + 1;
end if;
else
fastclkcntnext <= "000000";
And I was going to finish off with the outputs like this
if (fastclkcnt = 2 ) then -- PRECHARGE
mrasnext <= '0';
mcasnext <= '1';
mwenext <= '0';
mdqmnext <= '1';
elsif (fastclkcnt = 4 ) then -- REFRESH
mrasnext <= '0';
mcasnext <= '1';
mwenext <= '0';
mdqmnext <= '1';
elsif (fastclkcnt = 12 ) then -- REFRESH
mrasnext <= '0';
mcasnext <= '1';
mwenext <= '0';
mdqmnext <= '1';
.... and so on, and quite a few I might add
BUT one author I was reading stated that evertime I use a <= I am generating
another driver for the signal and that I should be doing something like
this:
mrasnext <= '0' when fastclkcnt = 2
'1' when fstclkcnt =4
'1' when fastclkcnt =12
Sort of grouping each output into one statement.
And but, what a drag, I have to re-figure the outputs at each clock every
time I play with a timing change.
Can somebody give me a strategy for 1) producing efficient firmware and 2)
looks clean and 3) can be changed easily.
Thanks in advance.
Brad
I am designing a specialized SDRAM controller and have a question about the
best way to set up some timing signals. I generally have a good idea about
what signals have to issued at certain clock times. I set up a rather long
clock cycle, separating the sync from the combo logic like this:
p1: process (fastclk3)
begin
if (fastclk3'event and fastclk3 = '1') then
fastclkcnt <= fastclkcntnext;
mras <= mrasnext;
.... and so on
p2: process (fastclkcnt)
begin
if ( fastclkcnt = 50 ) then
fastclkcntnext <= "011110"; --30
else
fastclkcntnext <= fastclkcnt + 1;
end if;
else
fastclkcntnext <= "000000";
And I was going to finish off with the outputs like this
if (fastclkcnt = 2 ) then -- PRECHARGE
mrasnext <= '0';
mcasnext <= '1';
mwenext <= '0';
mdqmnext <= '1';
elsif (fastclkcnt = 4 ) then -- REFRESH
mrasnext <= '0';
mcasnext <= '1';
mwenext <= '0';
mdqmnext <= '1';
elsif (fastclkcnt = 12 ) then -- REFRESH
mrasnext <= '0';
mcasnext <= '1';
mwenext <= '0';
mdqmnext <= '1';
.... and so on, and quite a few I might add
BUT one author I was reading stated that evertime I use a <= I am generating
another driver for the signal and that I should be doing something like
this:
mrasnext <= '0' when fastclkcnt = 2
'1' when fstclkcnt =4
'1' when fastclkcnt =12
Sort of grouping each output into one statement.
And but, what a drag, I have to re-figure the outputs at each clock every
time I play with a timing change.
Can somebody give me a strategy for 1) producing efficient firmware and 2)
looks clean and 3) can be changed easily.
Thanks in advance.
Brad