J
Jeffrey Dutky
Guest
I'm trying to understand the Samsung SMDK2410X demo board (for the
S3C2410 ARM microcontroller, see
http://www.samsung.com/Products/Semiconductor/SystemLSI/MobileSolutions/MobileASSP/MobileComputing/S3C2410X/S3C2410X.htm)
but I can't seem to figure out how the SDRAM is configured.
If I am reading the various SDRAM data sheets correctly, SDRAM chips
must be configured, at startup, before use (after applying power and
clock, issue a NOP condition for several hundred micro-seconds, then
issue prechage commands to all banks, then issue several refresh
cycles, finally issue a device configuration cycle to set the device
configuration register contents). I had thought that the CPLD in the
SMDK2410X schematic (U4) was responsible for configuring the SDRAMs at
startup, but it doesn't appear to have control over most of the
required signals (you need control over A0-A10, CAS, RAS, WE, and CS
to configure the SDRAM, but the CPLD only has access to A0-A3), and
appears to be used, mainly, to control the directional signal on the
data bus transcievers.
My question is: how are the SDRAMs configured on this board (or, in
general, with the S3C2410X MCU)?
1) Do the SDRAMs not really need any configuration (they start in an
acceptable mode)?
2) Does the S3C2410 issue the configuraiton signals after the MCUs
internal memory controller is configured?
3)Is there something else I am missing on the schematic?
The MCU User's Manual is less than helpfull on this topic: very little
expositive text, and what there is isn't all that well written. The
memory controller section is even terser than the rest of the
document.
S3C2410 ARM microcontroller, see
http://www.samsung.com/Products/Semiconductor/SystemLSI/MobileSolutions/MobileASSP/MobileComputing/S3C2410X/S3C2410X.htm)
but I can't seem to figure out how the SDRAM is configured.
If I am reading the various SDRAM data sheets correctly, SDRAM chips
must be configured, at startup, before use (after applying power and
clock, issue a NOP condition for several hundred micro-seconds, then
issue prechage commands to all banks, then issue several refresh
cycles, finally issue a device configuration cycle to set the device
configuration register contents). I had thought that the CPLD in the
SMDK2410X schematic (U4) was responsible for configuring the SDRAMs at
startup, but it doesn't appear to have control over most of the
required signals (you need control over A0-A10, CAS, RAS, WE, and CS
to configure the SDRAM, but the CPLD only has access to A0-A3), and
appears to be used, mainly, to control the directional signal on the
data bus transcievers.
My question is: how are the SDRAMs configured on this board (or, in
general, with the S3C2410X MCU)?
1) Do the SDRAMs not really need any configuration (they start in an
acceptable mode)?
2) Does the S3C2410 issue the configuraiton signals after the MCUs
internal memory controller is configured?
3)Is there something else I am missing on the schematic?
The MCU User's Manual is less than helpfull on this topic: very little
expositive text, and what there is isn't all that well written. The
memory controller section is even terser than the rest of the
document.