Scope Trigger for digital scope

[dlharmon]

I am designing a digital scope. This is just for learning. I already
have a nice 200MHz scope. I will be using a pair of ADS5410 ADCs
(80MHz 12 bit 1GHz analog bandwidth). I need to be able to deal with
signals above 40MHz so I will need some form of trigger. My idea is
to use a fast comparator for the trigger, and start integrating when
the trigger occurs. I could have the second ADC sample the voltage on
the integrator each clock cycle. The integrator reset would be
controlled from the FPGA. (Reset it a few cycles after the trigger and
hold it for a fixed number of cycles) This would allow the the exact
time the trigger occurs to be determined. Is there a better way of
doing this? Also, any suggestions for the trigger comparator? I would
like to be able to have AC/DC coupling and selectable positive/negative
slope.



Darrell Harmon
http://dlharmon.com/sbc.html

 

[James Meyer]

On 1 Feb 2005 15:51:40 -0800, "dlharmon" <mail@dlharmon.com> wroth:

I am designing a digital scope. This is just for learning. I already
have a nice 200MHz scope. I will be using a pair of ADS5410 ADCs
(80MHz 12 bit 1GHz analog bandwidth). I need to be able to deal with
signals above 40MHz so I will need some form of trigger.

Why not just run the A/D "balls to the wall" all the time, throw away
all but a little of the data, and do the triggering in soft(firm?)ware?

Jim

 

[Ken Smith]

In article <pau1011a2kltg787lb7aa2ksnheafq0fjr@4ax.com>,
John Larkin <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote:
[...]

Darrell's scheme sounds a lot simpler. ADCs are cheap these days.

Just stream samples from both ADCs into FIFOs. One ADC samples the
signal, the other samples a ramp. When you get a trigger, start the
ramp. Everything you need to know is now strolling through the FIFOs.

You could even use an FPGA and fast static RAM do looks sort of like a
FIFO but that averages the values into their correct time slots. Since he
is only after a 80MHz convert and 10nS times in RAMs and FPGAs are not to
hard to get these days, he could end up with something that doesn't have
to be processed very much after the fact.

--
--
kensmith@rahul.net forging knowledge

 

[keith]

On Thu, 03 Feb 2005 01:43:33 +0000, Ken Smith wrote:

In article <pau1011a2kltg787lb7aa2ksnheafq0fjr@4ax.com>,
John Larkin <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote:
[...]
Darrell's scheme sounds a lot simpler. ADCs are cheap these days.

Just stream samples from both ADCs into FIFOs. One ADC samples the
signal, the other samples a ramp. When you get a trigger, start the
ramp. Everything you need to know is now strolling through the FIFOs.

You could even use an FPGA and fast static RAM do looks sort of like a
FIFO but that averages the values into their correct time slots. Since he
is only after a 80MHz convert and 10nS times in RAMs and FPGAs are not to
hard to get these days, he could end up with something that doesn't have
to be processed very much after the fact.

Stream the data through Xilinx' SRL16s (freebie 16bit FIFOs). Pick off
the output where you want.

--
Keith

 

[John Larkin]

On 3 Feb 2005 02:43:57 -0800, bill.sloman@ieee.org wrote:

If you want to test for non-linearities you'd want two independently
programmable 100195's in series, though a random trigger source might
work as well if you had the time to build up statisically significant
histograms of the number of times each delay interval was hit ...
Fun stuff.

Histogramming the ADC codes is a good way to estimate ramp
nonlinearity. Heterodyne walking can work, too. But the bottom line is
RMS jitter.

I've also tended to make fast ramps by charging a cap with a cc
source. But maybe it's time to revisit the opamp integrator; for ramps
in the 10s of ns, fast enough opamps are probably now available, and
problems with nonlinear junction capacitances - the bane of fast ramps
- theoretically disappear.

John

-------
Bill Sloman, Nijmegen

 

[dlharmon]

Do you really need exact or is very good repeatability what you are
after?

repeatability is all that matters here. If it is consistent, I can fix
it with software. Thanks for the ideas.

Darrell Harmon

 

[dlharmon]

Thanks for all the info you have provided. I have gotten more ideas
than I ever expected from this newsgroup. I think I will go with the
integrator. The idea to sample the ramp on the second cycle after the
trigger is excellent. Hopefully 12.5ns is long enough for it to settle
to a decent ramp.

I am making this scope modular. The input and trigger will be modules
(think plug in scope), so I can experiment with different techniques.
I have much more design work ahead of me, but I hope to get this going
soon. I will post a link to the schematics and source code when they
are done.

Darrell Harmon

 

[John Larkin]

On Sat, 05 Feb 2005 16:08:11 -0800, mike <spamme0@netscape.net> wrote:

There are some simple things you can do if you don't need very fine
interpolation. Send the trigger down a tapped delay line and latch the
outputs on the clock edge.
mike

Did that! It was a real pain to adjust, though.

http://www.highlandtechnology.com/DSS/M680DS.html

John