problem with rising clock edge

R

rekz

Guest
I have a problem with the code below. The problem is that the output,
which is ForwardA and ForwardB is not updated not on the rising clock
edge rather than on the next rising clock edge... why is this?? How do
I resolve so that the output is updated on the same positive rising
clock edge?

Here's what I mean:

always @(posedge Clk) begin

ForwardA = 0;
ForwardB = 0;

//EX Hazard
if (EXMEMRegWrite == 1) begin
if (EXMEMrd != 0)
if (EXMEMrd == IDEXrs)
ForwardA = 2'b10;
if (EXMEMrd == IDEXrt && IDEXTest == 0)
ForwardB = 2'b10;
end


//MEM Hazard

if (MEMWBRegWrite == 1) begin
if (MEMWBrd != 0) begin
if (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrs)))
if (MEMWBrd == IDEXrs)
ForwardA = 2'b01;
if (IDEXTest == 0) begin
if (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd ==
IDEXrt)))
if (MEMWBrd == IDEXrt)
ForwardB = 2'b01;
end
end
end

end
 
On Tue, 4 May 2010 18:14:57 -0700 (PDT), rekz <aditya15417@gmail.com>
wrote:

I have a problem with the code below. The problem is that the output,
which is ForwardA and ForwardB is not updated not on the rising clock
edge rather than on the next rising clock edge... why is this?? How do
I resolve so that the output is updated on the same positive rising
clock edge?

Here's what I mean:

always @(posedge Clk) begin

ForwardA = 0;
ForwardB = 0;

//EX Hazard
if (EXMEMRegWrite == 1) begin
if (EXMEMrd != 0)
if (EXMEMrd == IDEXrs)
ForwardA = 2'b10;
if (EXMEMrd == IDEXrt && IDEXTest == 0)
ForwardB = 2'b10;
end
Click to expand...
I think you're asking why ForwardA doesn't get updated in the same
cycle as EXMEMRegWrite becomes 1 (and some other conditions). If
that's the case, the reason is that at that point in time it is too
late for ForwardA to change its value. Assuming EXMEMRegWrite is
generated by the same "Clk", ForwardA can be changed only on the next
edge. This is what makes a shift register work. If you want
combinational register forwarding (which adds to the worst case path)
then you should say

always @(*)
....

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com
 
On May 4, 10:41 pm, Muzaffer Kal <k...@dspia.com> wrote:
On Tue, 4 May 2010 18:14:57 -0700 (PDT), rekz <aditya15...@gmail.com
wrote:





I have a problem with the code below. The problem is that the output,
which is ForwardA and ForwardB is not updated not on the rising clock
edge rather than on the next rising clock edge... why is this?? How do
I resolve so that the output is updated on the same positive rising
clock edge?

Here's what I mean:

always @(posedge Clk) begin

ForwardA = 0;
ForwardB = 0;

//EX Hazard
if (EXMEMRegWrite == 1) begin
if (EXMEMrd != 0)
   if (EXMEMrd == IDEXrs)
       ForwardA = 2'b10;
  if (EXMEMrd == IDEXrt && IDEXTest == 0)
       ForwardB = 2'b10;
end

I think you're asking why ForwardA doesn't get updated in the same
cycle as EXMEMRegWrite becomes 1 (and some other conditions). If
that's the case, the reason is that at that point in time it is too
late for ForwardA to change its value. Assuming EXMEMRegWrite is
generated by the same "Clk", ForwardA can be changed only on the next
edge. This is what makes a shift register work. If you want
combinational register forwarding (which adds to the worst case path)
then you should say

always @(*)
...

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com
Click to expand...
Yes, that is exactly what I am saying... I've used always@(*) but as
you said the synthesis result wasn't what I expected.
Is there a way to still to do this without having a worse path
 
On May 5, 6:13 am, rekz <aditya15...@gmail.com> wrote:
On May 4, 10:41 pm, Muzaffer Kal <k...@dspia.com> wrote:





On Tue, 4 May 2010 18:14:57 -0700 (PDT), rekz <aditya15...@gmail.com
wrote:

I have a problem with the code below. The problem is that the output,
which is ForwardA and ForwardB is not updated not on the rising clock
edge rather than on the next rising clock edge... why is this?? How do
I resolve so that the output is updated on the same positive rising
clock edge?

Here's what I mean:

always @(posedge Clk) begin

ForwardA = 0;
ForwardB = 0;

//EX Hazard
if (EXMEMRegWrite == 1) begin
if (EXMEMrd != 0)
   if (EXMEMrd == IDEXrs)
       ForwardA = 2'b10;
  if (EXMEMrd == IDEXrt && IDEXTest == 0)
       ForwardB = 2'b10;
end

I think you're asking why ForwardA doesn't get updated in the same
cycle as EXMEMRegWrite becomes 1 (and some other conditions). If
that's the case, the reason is that at that point in time it is too
late for ForwardA to change its value. Assuming EXMEMRegWrite is
generated by the same "Clk", ForwardA can be changed only on the next
edge. This is what makes a shift register work. If you want
combinational register forwarding (which adds to the worst case path)
then you should say

always @(*)
...

--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Yes, that is exactly what I am saying... I've used always@(*) but as
you said the synthesis result wasn't what I expected.
Is there a way to still to do this without having a worse path- Hide quoted text -

- Show quoted text -
Click to expand...
I was able to resolve this using wires, assign, and ternary operators.
Thanks
 
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