Power on problems

[etrac]

We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power
seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO
are asking too much current (> 1.5A) for a long time. This occurs
approximatively 1 second after the power is on.
We have a current limitation power supply, so the VccAux/VccO voltage
fall at nearly 1.5V, that is to say that the FPGA needs very much than
1.5A ..

Does anybody ever had this kind of issue ? Or do you know a possible
cause of this event ?

 

[Austin Lesea]

etrac,

Sounds broken.

Virtex II and II Pro have no power on current surges whatsoever.

Are you sure that you are not programming it to do something? Like all
IOs are DCI HSTL input terminations (~54 mW each IO, 17 mA)? One hundred
of these IOs programmed this way makes ~ 1.7 amperes, and 5.4 watts.

The delay one one second is billions of times faster than the logic works,
so it is unlikely it is the part doing something, it is more likely
programming has just completed.....

Open a hotline case.

Austin

etrac wrote:

We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power
seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO
are asking too much current (> 1.5A) for a long time. This occurs
approximatively 1 second after the power is on.
We have a current limitation power supply, so the VccAux/VccO voltage
fall at nearly 1.5V, that is to say that the FPGA needs very much than
1.5A ..

Does anybody ever had this kind of issue ? Or do you know a possible
cause of this event ?

 

[etrac]

At poweron I think the FPGA is not programmed ! It is in boundary scan
mode (pins M0-M1-M2), but I can't access to it with JTAG because the
voltage isn't sufficient. So I'm sure the FPGA is free !

There are some other components on the board, such as DSPs, they have
independant power supplys, but they are connected on some FPGA IOs. Do
you think they can disturb the FPGA at poweron ? My meaning was that
the FPGA IOs were tristated at poweron, nevertheless could they be
active when core or IO voltage are not yet stabilized ?

etrac

Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F5F3C37.9758AF5F@xilinx.com>...

etrac,

Sounds broken.

Virtex II and II Pro have no power on current surges whatsoever.

Are you sure that you are not programming it to do something? Like all
IOs are DCI HSTL input terminations (~54 mW each IO, 17 mA)? One hundred
of these IOs programmed this way makes ~ 1.7 amperes, and 5.4 watts.

The delay one one second is billions of times faster than the logic works,
so it is unlikely it is the part doing something, it is more likely
programming has just completed.....

Open a hotline case.

Austin

etrac wrote:

We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power
seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO
are asking too much current (> 1.5A) for a long time. This occurs
approximatively 1 second after the power is on.
We have a current limitation power supply, so the VccAux/VccO voltage
fall at nearly 1.5V, that is to say that the FPGA needs very much than
1.5A ..

Does anybody ever had this kind of issue ? Or do you know a possible
cause of this event ?

 

[etrac]

Hi,
We have found the problem and this might interest somebody here so I
explain the reasons of the voltage falling : It was simply because we
put too many bypassing capacitors around the FPGA ! The virtex II
datasheet is asking for many capacitors to have good linearity in the
fpga voltages, but our power supply was not enough strong to support
the current when we power on the board.

Etrac.


etraq@yahoo.fr (etrac) wrote in message news:<c99b95c7.0309150215.32a211e8@posting.google.com>...

At poweron I think the FPGA is not programmed ! It is in boundary scan
mode (pins M0-M1-M2), but I can't access to it with JTAG because the
voltage isn't sufficient. So I'm sure the FPGA is free !

There are some other components on the board, such as DSPs, they have
independant power supplys, but they are connected on some FPGA IOs. Do
you think they can disturb the FPGA at poweron ? My meaning was that
the FPGA IOs were tristated at poweron, nevertheless could they be
active when core or IO voltage are not yet stabilized ?

etrac

Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F5F3C37.9758AF5F@xilinx.com>...
etrac,

Sounds broken.

Virtex II and II Pro have no power on current surges whatsoever.

Are you sure that you are not programming it to do something? Like all
IOs are DCI HSTL input terminations (~54 mW each IO, 17 mA)? One hundred
of these IOs programmed this way makes ~ 1.7 amperes, and 5.4 watts.

The delay one one second is billions of times faster than the logic works,
so it is unlikely it is the part doing something, it is more likely
programming has just completed.....

Open a hotline case.

Austin

etrac wrote:

We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power
seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO
are asking too much current (> 1.5A) for a long time. This occurs
approximatively 1 second after the power is on.
We have a current limitation power supply, so the VccAux/VccO voltage
fall at nearly 1.5V, that is to say that the FPGA needs very much than
1.5A ..

Does anybody ever had this kind of issue ? Or do you know a possible
cause of this event ?

 

[Jim Granville]

etrac wrote:

Hi,
We have found the problem and this might interest somebody here so I
explain the reasons of the voltage falling : It was simply because we
put too many bypassing capacitors around the FPGA ! The virtex II
datasheet is asking for many capacitors to have good linearity in the
fpga voltages, but our power supply was not enough strong to support
the current when we power on the board.

Etrac.
etrac wrote:

We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power
seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO
are asking too much current (> 1.5A) for a long time. This occurs
approximatively 1 second after the power is on.
We have a current limitation power supply, so the VccAux/VccO voltage
fall at nearly 1.5V, that is to say that the FPGA needs very much than
1.5A ..

This does not quite 'gel' - you are saying lowering the Total C alone
solved the issue ?

That suggests a dV/dT limit, but times in the order of 1 second ?
It may be a power-sequencing effect, which total C would affect.

-jg

 

[etrac]

Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3F8DBF2B.2595@designtools.co.nz>...

etrac wrote:

Hi,
We have found the problem and this might interest somebody here so I
explain the reasons of the voltage falling : It was simply because we
put too many bypassing capacitors around the FPGA ! The virtex II
datasheet is asking for many capacitors to have good linearity in the
fpga voltages, but our power supply was not enough strong to support
the current when we power on the board.

Etrac.
etrac wrote:

We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power
seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO
are asking too much current (> 1.5A) for a long time. This occurs
approximatively 1 second after the power is on.
We have a current limitation power supply, so the VccAux/VccO voltage
fall at nearly 1.5V, that is to say that the FPGA needs very much than
1.5A ..

This does not quite 'gel' - you are saying lowering the Total C alone
solved the issue ?

That suggests a dV/dT limit, but times in the order of 1 second ?
It may be a power-sequencing effect, which total C would affect.

-jg

Our power supply is current limited (2 Amps), and at poweron
capacitors were asking too many current for the power supply. So we
were in overcurrent mode. That was the same problem with our
laboratory power supplies, with a current limitation ..

Etrac

 

[rickman]

etrac wrote:

Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3F8DBF2B.2595@designtools.co.nz>...
etrac wrote:

Hi,
We have found the problem and this might interest somebody here so I
explain the reasons of the voltage falling : It was simply because we
put too many bypassing capacitors around the FPGA ! The virtex II
datasheet is asking for many capacitors to have good linearity in the
fpga voltages, but our power supply was not enough strong to support
the current when we power on the board.

Etrac.
etrac wrote:

We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power
seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO
are asking too much current (> 1.5A) for a long time. This occurs
approximatively 1 second after the power is on.
We have a current limitation power supply, so the VccAux/VccO voltage
fall at nearly 1.5V, that is to say that the FPGA needs very much than
1.5A ..

This does not quite 'gel' - you are saying lowering the Total C alone
solved the issue ?

That suggests a dV/dT limit, but times in the order of 1 second ?
It may be a power-sequencing effect, which total C would affect.

-jg

Our power supply is current limited (2 Amps), and at poweron
capacitors were asking too many current for the power supply. So we
were in overcurrent mode. That was the same problem with our
laboratory power supplies, with a current limitation ..

Etrac

Isn't that a common mode during power on? Exactly what problem does
this cause? Are you saying that the current causes a voltage foldback
so that the rise is not monotonic? If so, your problem is not the
capacitors, it is the foldback current limiting. I find it hard to
imagine the caps on a board having more total capacitance than a power
supply. But I guess you may be working with an on board DC/DC with 100
uF or less.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

 

[etrac]

rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F93E4A8.C68E3142@yahoo.com>...

etrac wrote:

Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3F8DBF2B.2595@designtools.co.nz>...
etrac wrote:

Hi,
We have found the problem and this might interest somebody here so I
explain the reasons of the voltage falling : It was simply because we
put too many bypassing capacitors around the FPGA ! The virtex II
datasheet is asking for many capacitors to have good linearity in the
fpga voltages, but our power supply was not enough strong to support
the current when we power on the board.

Etrac.
etrac wrote:

We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power
seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO
are asking too much current (> 1.5A) for a long time. This occurs
approximatively 1 second after the power is on.
We have a current limitation power supply, so the VccAux/VccO voltage
fall at nearly 1.5V, that is to say that the FPGA needs very much than
1.5A ..

This does not quite 'gel' - you are saying lowering the Total C alone
solved the issue ?

That suggests a dV/dT limit, but times in the order of 1 second ?
It may be a power-sequencing effect, which total C would affect.

-jg

Our power supply is current limited (2 Amps), and at poweron
capacitors were asking too many current for the power supply. So we
were in overcurrent mode. That was the same problem with our
laboratory power supplies, with a current limitation ..

Etrac

Isn't that a common mode during power on? Exactly what problem does
this cause? Are you saying that the current causes a voltage foldback
so that the rise is not monotonic? If so, your problem is not the
capacitors, it is the foldback current limiting. I find it hard to
imagine the caps on a board having more total capacitance than a power
supply. But I guess you may be working with an on board DC/DC with 100
uF or less.

--

Rick "rickman" Collins

We use Motorola QuiccSupply products to power the FPGA, they have two
protections : overcurrent protection and undervoltage lockout. The
first limits the current, the second disables the power if the voltage
is not in the good range (checked every 100ms). That's why if C is big
the power supply can't raise the voltage quickly and the QuiccSupply
goes in undervoltage lockout.

That's true that if the Power supply doesn't have any undervoltage
lockout capability we did not have such problems .. Nevertheless
Virtex II documentation says that at power on, each supply line (VCCO
VCCAUX and VCCINT) has to be stable quickly (< 200 ms if I remember
well), otherwise the component will need more current to power on.
So I think that having too many bypassing capacitors may affect the
power on. Of course this event depends on the power supply used ..

Etrac

 

[Austin Lesea]

<50 ms.

We do not test outside of 250 us to 50 ms, so do not use the part there unless you wish to chaacterize it's
behavior.

There is no high current behavior on Virtex II, II Pro, II Pro-X (10 Gbs Virtex II Pro announced today), Spartan
III.

Austin

etrac wrote:

rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F93E4A8.C68E3142@yahoo.com>...
etrac wrote:

Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3F8DBF2B.2595@designtools.co.nz>...
etrac wrote:

Hi,
We have found the problem and this might interest somebody here so I
explain the reasons of the voltage falling : It was simply because we
put too many bypassing capacitors around the FPGA ! The virtex II
datasheet is asking for many capacitors to have good linearity in the
fpga voltages, but our power supply was not enough strong to support
the current when we power on the board.

Etrac.
etrac wrote:

We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power
seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO
are asking too much current (> 1.5A) for a long time. This occurs
approximatively 1 second after the power is on.
We have a current limitation power supply, so the VccAux/VccO voltage
fall at nearly 1.5V, that is to say that the FPGA needs very much than
1.5A ..

This does not quite 'gel' - you are saying lowering the Total C alone
solved the issue ?

That suggests a dV/dT limit, but times in the order of 1 second ?
It may be a power-sequencing effect, which total C would affect.

-jg

Our power supply is current limited (2 Amps), and at poweron
capacitors were asking too many current for the power supply. So we
were in overcurrent mode. That was the same problem with our
laboratory power supplies, with a current limitation ..

Etrac

Isn't that a common mode during power on? Exactly what problem does
this cause? Are you saying that the current causes a voltage foldback
so that the rise is not monotonic? If so, your problem is not the
capacitors, it is the foldback current limiting. I find it hard to
imagine the caps on a board having more total capacitance than a power
supply. But I guess you may be working with an on board DC/DC with 100
uF or less.

--

Rick "rickman" Collins

We use Motorola QuiccSupply products to power the FPGA, they have two
protections : overcurrent protection and undervoltage lockout. The
first limits the current, the second disables the power if the voltage
is not in the good range (checked every 100ms). That's why if C is big
the power supply can't raise the voltage quickly and the QuiccSupply
goes in undervoltage lockout.

That's true that if the Power supply doesn't have any undervoltage
lockout capability we did not have such problems .. Nevertheless
Virtex II documentation says that at power on, each supply line (VCCO
VCCAUX and VCCINT) has to be stable quickly (< 200 ms if I remember
well), otherwise the component will need more current to power on.
So I think that having too many bypassing capacitors may affect the
power on. Of course this event depends on the power supply used ..

Etrac

 

[rickman]

etrac wrote:

rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F93E4A8.C68E3142@yahoo.com>...
Isn't that a common mode during power on? Exactly what problem does
this cause? Are you saying that the current causes a voltage foldback
so that the rise is not monotonic? If so, your problem is not the
capacitors, it is the foldback current limiting. I find it hard to
imagine the caps on a board having more total capacitance than a power
supply. But I guess you may be working with an on board DC/DC with 100
uF or less.

--

Rick "rickman" Collins

We use Motorola QuiccSupply products to power the FPGA, they have two
protections : overcurrent protection and undervoltage lockout. The
first limits the current, the second disables the power if the voltage
is not in the good range (checked every 100ms). That's why if C is big
the power supply can't raise the voltage quickly and the QuiccSupply
goes in undervoltage lockout.

That's true that if the Power supply doesn't have any undervoltage
lockout capability we did not have such problems .. Nevertheless
Virtex II documentation says that at power on, each supply line (VCCO
VCCAUX and VCCINT) has to be stable quickly (< 200 ms if I remember
well), otherwise the component will need more current to power on.
So I think that having too many bypassing capacitors may affect the
power on. Of course this event depends on the power supply used ..

Etrac

But if you do the math with the magnitude of current, voltage and times
you will find that it requires an *enormous* amount of capacitance to
obstruct your ramp time. Using 5 volts, 2 Amps and 50 mS, I get 20,000
uF. Clearly anything in a typical range of capacitance (~100-200 uF)
should not adversely impact your power on ramp unless all the supply
current is going through the chips. Are the chips drawing enough
current at power up that the supply is nearly current limited?

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX