PLL tricks

[Bill Sloman]

On 29/09/2014 2:04 AM, John Larkin wrote:

On Sun, 28 Sep 2014 08:07:38 +0100, "Kevin Aylward"
ExtractkevinRemove@kevinaylward.co.uk> wrote:

"John Larkin" wrote in message
news:4qie2alha115etc597v39e52nvrtnvav0t@4ax.com...


Consider this:

If we square up the 10 MHz reference, and the 155.52 MHz oscillator
were somehow locked to it, the edges line up at 80 KHz, namely every
12.5 us. So the bangbang phase detector only delivers one bit of
information (namely early/late) 80K times per second. That may be too
noisy to discipline a cheap 155 MHz VCXO.

Why not just use a non-cheap 155.52 MHz VCXO?

There aren't all that many 155.52's around.

Correct, but there are wades of exact 38.88 MHz and 19.44 MHz XTAL VCXOs
about. I know, my current OSC ASIC uses them

There are also x4 multiplier chips that are designed to solve this
particular 155.52 MHz problem from those frequencies.

This is bog standard. Obtain a 155.52 MHz VCXO from a (tank) multiplied up
from 38.88 MHz or 19.44 MHz VCXO

The X4 multiplier would have to produce edges that are strictly
periodic to picoseconds. Can that be done?

It's done in Rubidium and Caesium atomic clocks. The very precise
microwave frequency that messes with the hyperfine transitions would be
smeared out in frequency if edges weren't periodic to picoseconds.

CTS does make a surfmount 155.52 fundamental VCXO that claims very low
jitter. Samples are coming, I think.

Comforting.

--
Bill Sloman, Sydney

 

[Tauno Voipio]

On 28.9.14 19:06, John Larkin wrote:

On Sun, 28 Sep 2014 13:33:50 +0300, Tauno Voipio
tauno.voipio@notused.fi.invalid> wrote:

On 28.9.14 11:45, rickman wrote:
On 9/28/2014 3:23 AM, Bill Sloman wrote:
On 28/09/2014 2:11 PM, rickman wrote:

The device you link to is one (or one very like it) used by a friend in
a unit he built for the Naval Observatory to provide a 1 PPS output from
their newest atomic clock. Seems this clock uses a 100 MHz output as
it's timing reference.

Have you looked at the way they work? The Rubidium standard uses a
6,834.682,610.904 Hz microwave oscillator (6.9GHz) to hit the relevant
atomic hyperfine transition, and seems to get it by multiplying up a
suitable frequency from a quartz-crystal-based VCXO. Quite where an
MC100EP195 would fit into that isn't clear.

My friend didn't build the atomic clock. He built the 1 pps circuit. I
think I described it here once already. The clock has a 100 MHz output.
They have a number of atomic clocks with different accuracies and
receive signals from other clocks around the world. These are all fed
into a Kalman filter which appears to be able to improve its result
using even the poorer accuracy signals.

I guess the filter is using the 1 ppm signal because my friend's circuit
received the 1 ppm from the filter to pick an edge of the 100 MHz clock
to sync his 1 pps to. The circuit then applied a phase adjustment using
this chip (or another one like it) to get the 1 pps in sync with the
signal from the Kalman filter. I'm pretty sure once it was solidly in
sync with both the 100 MHz from the clock and the 1 pps from the Kalman
filter it was then used as one of the sources for the Kalman filter.

In the clock, how do they detect the difference in frequency of the
multiplied VCXO and the Rubidium transition?


The classical method is to sweep the VCXO slightly and observe the
changes in the Rb cell absorption. A servo balances the sweep to
be symmetrical about the sweet point.

IIRC, there was an article about it in an older HP Journal.

https://dl.dropboxusercontent.com/u/53724080/Gear/Efratom.pdf

Thanks John. So the wiggle is done by phase modulation in the
multiplier chain, so the VCXO stays clean.

--

-TV

 

[Kevin Aylward]

"John Larkin" wrote in message
news:q7cg2aho3elvno5q8ujko8dau4bdg0u8l9@4ax.com...

On Sun, 28 Sep 2014 08:07:38 +0100, "Kevin Aylward"
<ExtractkevinRemove@kevinaylward.co.uk> wrote:

"John Larkin" wrote in message
news:4qie2alha115etc597v39e52nvrtnvav0t@4ax.com...


Consider this:

If we square up the 10 MHz reference, and the 155.52 MHz oscillator
were somehow locked to it, the edges line up at 80 KHz, namely every
12.5 us. So the bangbang phase detector only delivers one bit of
information (namely early/late) 80K times per second. That may be too
noisy to discipline a cheap 155 MHz VCXO.

Why not just use a non-cheap 155.52 MHz VCXO?

There aren't all that many 155.52's around.

Correct, but there are wades of exact 38.88 MHz and 19.44 MHz XTAL VCXOs
about. I know, my current OSC ASIC uses them

There are also x4 multiplier chips that are designed to solve this
particular 155.52 MHz problem from those frequencies.

This is bog standard. Obtain a 155.52 MHz VCXO from a (tank) multiplied up
from 38.88 MHz or 19.44 MHz VCXO

The X4 multiplier would have to produce edges that are strictly
periodic to picoseconds. Can that be done?

Well....my current research tells me that a X9 of a 200MHz to 1.8GHz can get
you < 25 femto seconds jitter integrated over the 12KH to 20MHz. Tuning
doesnt have a big impact on noise, its more of an effect on subharmics of
the 1.8GHz.

Cadence spits out the individual jitter from every edge. Its low.

I have yet to experiment for a 38.88 MHz X 4 , but it can be extrapolated
from the above

CTS does make a surfmount 155.52 fundamental VCXO that claims very low
jitter. Samples are coming, I think.

A high frequency oscillator, e.g. a SAW may be the way to go. Its hard to
get good performance in a xtal at that frequency, but something I have been
looking at.

My point is that, if a higher frequency oscillator is a VCO locked to a
reference as a given, then generating that equivalent higher frequency VCO
by multiplying up a lower frequency in a tank, can pretty much achieve close
to the theoretical noise of such a multiplication. This is not really
debatable. The tank may well have some low frequency phase drift, but it is
assumed to be in a loop to correct for that. HF noise is not really a
problem for the multiplier bit. The input oscillator dominates. In fact, 100
ohm at the input of the multiplier dominates the noise floor.

For GHz+, you need the lower stability HF oscillators, multiplying up from
50MHz would be too noisy.

Seriously, designing for low phase noise/jitter is pretty much impossible
without design tools, imo. Have you though about getting some?

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

On Sunday, September 28, 2014 7:54:37 PM UTC-4, Gerhard Hoffmann wrote:

Am 28.09.2014 um 18:04 schrieb John Larkin:

The X4 multiplier would have to produce edges that are strictly
periodic to picoseconds. Can that be done?

Seems like you don't use the pointers that I provide.

If it has been done it must be possible.

http://www.wenzel.com/wp-content/uploads/Sub-pico-Multiplier.pdf

That is an excellent reference. Thank you.

I'd forgotten about Wenzel's multipliers.

> Wenzel is one of the prime sources in precision oscillators.

Cheers,
James Arthur

 

[Kevin Aylward]

wrote in message
news:6e99708b-a765-4c44-a376-eaff0dacbdd7@googlegroups.com...

On Sunday, September 28, 2014 3:07:38 AM UTC-4, Kevin Aylward wrote:

"John Larkin" wrote:
dagmargoo...@yahoo.com wrote:
John Larkin wrote:

If we square up the 10 MHz reference, and the 155.52 MHz oscillator
were somehow locked to it, the edges line up at 80 KHz, namely every
12.5 us. So the bangbang phase detector only delivers one bit of
information (namely early/late) 80K times per second. That may be too
noisy to discipline a cheap 155 MHz VCXO.

Why not just use a non-cheap 155.52 MHz VCXO?

There aren't all that many 155.52's around.

Correct, but there are wades of exact 38.88 MHz and 19.44 MHz XTAL VCXOs
about. I know, my current OSC ASIC uses them

There are also x4 multiplier chips that are designed to solve this
particular 155.52 MHz problem from those frequencies.

Or just get a custom 155.52 MHz super-fine VCXO. I don't think they're
even very expensive, it's on the order of getting a custom crystal.

There are 155.52 out there, and that may be the best solution

This is bog standard. Obtain a 155.52 MHz VCXO from a (tank) multiplied up
from 38.88 MHz or 19.44 MHz VCXO.

As someone who has made 908 MHz from 14.4MHz in production with a
multi-stage tank-based multiplier, I still don't understand how a
tank x4 multiplier can ensure John accurate phase.

Its in a loop. The (38.88 x 4) is just one oscillator. It has to be better
than an LC oscillator at 150MHz locked on to its input of 10 MHz. Any LC
variation give direct frequency modulation, which is way, way worse than a
tank drifting a bit. The output frequency of a tank must still be exactly
equal to its input for a fixed change in component values. A tank oscillator
will have a fixed steady state shift.

You bang the tank and it rings--so far so good. But if the tank isn't
*perfectly* tuned, it rings off frequency, and the 'ring' cycles wander
off phase, right?

You do know that tank multiplied oscillators are industry used standard
methods in achieving low phase noise in preference to PLLs?

You'd need a varactor, phase-detector, and a feedback loop to keep the
tank tuned perfectly true, AFAICT, introducing additional problems on
several fronts.

The tank does not have to be perfectly tuned. The tuning doesn't effect the
phase noise. It effects the sub harmonics. For example, tuning at 25 deg C,
then moving to -40 deg, might lose you about 6db from a -50dbc close in
subharmonic.

Again, the VCO is in a loop for its close in stability, e. where temperature
change with produce a transient phase change.

ISTM a custom 155.52 MHz VCXO is literally rock-stable, provides the
best performance attainable, and eliminates a great deal of design
risk and nuisance.

It does not necessarily give the "best" performance. Lower frequency xtals
have much better stability. It might be the "optimum" solution


Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

Kevin wrote:

dagmargoo...@yahoo.com wrote:
Kevin wrote:
There are also x4 multiplier chips that are designed to solve this
particular 155.52 MHz problem from those frequencies.

Or just get a custom 155.52 MHz super-fine VCXO. I don't think they're
even very expensive, it's on the order of getting a custom crystal.

There are 155.52 out there, and that may be the best solution

This is bog standard. Obtain a 155.52 MHz VCXO from a (tank) multiplied up
from 38.88 MHz or 19.44 MHz VCXO.

As someone who has made 908 MHz from 14.4MHz in production with a
multi-stage tank-based multiplier, I still don't understand how a
tank x4 multiplier can ensure John accurate phase.

Its in a loop.

That's the part I don't understand, though Gerhard's Wenzel paper helps.

The multiplier topologies I've most seen are class-C amps driving a pulse
into an L-C tank. The tank then rings off, until the next pulse arrives.

My 3x multiplier tanks would've gladly rung at 2*(f_in) if they were so
tuned, with zero-crossings off the 3x placements by a country mile.

.-.
_| |_ .----+-----.
| | |
>---||---' ) ---
) ---
) | ^
| +------> / \/\.
=== |
---
---
|
===

In John's case, that would have been a horrific phase error.

The (38.88 x 4) is just one oscillator. It has to be better
than an LC oscillator at 150MHz locked on to its input of 10 MHz.
Any LC variation give direct frequency modulation, which is way,
way worse than a tank drifting a bit. The output frequency of a
tank must still be exactly equal to its input for a fixed change
in component values. A tank oscillator will have a fixed steady
state shift.

Right. I'm not suggesting a 155.52 MHz L-C oscillator! I mean a
155.52 MHz 5th-overtone quartz crystal oscillator, Q>=70k.

You bang the tank and it rings--so far so good. But if the tank isn't
*perfectly* tuned, it rings off frequency, and the 'ring' cycles wander
off phase, right?

You do know that tank multiplied oscillators are industry used standard
methods in achieving low phase noise in preference to PLLs?

No, I didn't, though I believe you.

You'd need a varactor, phase-detector, and a feedback loop to keep the
tank tuned perfectly true, AFAICT, introducing additional problems on
several fronts.

The tank does not have to be perfectly tuned. The tuning doesn't effect the
phase noise. It effects the sub harmonics. For example, tuning at 25 deg C,
then moving to -40 deg, might lose you about 6db from a -50dbc close in
subharmonic.

I'm looking at it in the time domain, and can only imagine you must be
thinking of a different topology than I am.

Wenzel's topology changes things, since it makes 2f very accurately from a
sine wave, not relying on a tuned tank. Ditto 3f, I *think*.

(Wenzel's odd-multiplier might be an excellent low-noise way to square-up
the 10MHz reference.)

Again, the VCO is in a loop for its close in stability, e. where temperature
change with produce a transient phase change.

ISTM a custom 155.52 MHz VCXO is literally rock-stable, provides the
best performance attainable, and eliminates a great deal of design
risk and nuisance.

It does not necessarily give the "best" performance. Lower frequency xtals
have much better stability. It might be the "optimum" solution.

By "stability" I assume you mean df/dT, and I'm assuming the whole thing
will have to be ovenized, making that less important.

Thanks for the feedback.

Cheers,
James Arthur

 

[John Larkin]

On Sun, 28 Sep 2014 21:05:58 +0100, "Kevin Aylward"
<ExtractkevinRemove@kevinaylward.co.uk> wrote:

"John Larkin" wrote in message
news:q7cg2aho3elvno5q8ujko8dau4bdg0u8l9@4ax.com...

On Sun, 28 Sep 2014 08:07:38 +0100, "Kevin Aylward"
ExtractkevinRemove@kevinaylward.co.uk> wrote:

"John Larkin" wrote in message
news:4qie2alha115etc597v39e52nvrtnvav0t@4ax.com...


Consider this:

If we square up the 10 MHz reference, and the 155.52 MHz oscillator
were somehow locked to it, the edges line up at 80 KHz, namely every
12.5 us. So the bangbang phase detector only delivers one bit of
information (namely early/late) 80K times per second. That may be too
noisy to discipline a cheap 155 MHz VCXO.

Why not just use a non-cheap 155.52 MHz VCXO?

There aren't all that many 155.52's around.

Correct, but there are wades of exact 38.88 MHz and 19.44 MHz XTAL VCXOs
about. I know, my current OSC ASIC uses them

There are also x4 multiplier chips that are designed to solve this
particular 155.52 MHz problem from those frequencies.

This is bog standard. Obtain a 155.52 MHz VCXO from a (tank) multiplied up
from 38.88 MHz or 19.44 MHz VCXO

The X4 multiplier would have to produce edges that are strictly
periodic to picoseconds. Can that be done?

Well....my current research tells me that a X9 of a 200MHz to 1.8GHz can get
you < 25 femto seconds jitter integrated over the 12KH to 20MHz. Tuning
doesnt have a big impact on noise, its more of an effect on subharmics of
the 1.8GHz.

Cadence spits out the individual jitter from every edge. Its low.

I have yet to experiment for a 38.88 MHz X 4 , but it can be extrapolated
from the above

CTS does make a surfmount 155.52 fundamental VCXO that claims very low
jitter. Samples are coming, I think.

A high frequency oscillator, e.g. a SAW may be the way to go. Its hard to
get good performance in a xtal at that frequency, but something I have been
looking at.

My point is that, if a higher frequency oscillator is a VCO locked to a
reference as a given, then generating that equivalent higher frequency VCO
by multiplying up a lower frequency in a tank, can pretty much achieve close
to the theoretical noise of such a multiplication. This is not really
debatable. The tank may well have some low frequency phase drift, but it is
assumed to be in a loop to correct for that. HF noise is not really a
problem for the multiplier bit. The input oscillator dominates. In fact, 100
ohm at the input of the multiplier dominates the noise floor.

For GHz+, you need the lower stability HF oscillators, multiplying up from
50MHz would be too noisy.

Seriously, designing for low phase noise/jitter is pretty much impossible
without design tools, imo. Have you though about getting some?

No; I plan to buy the oscillator. XO experts can design better
oscillators than I can.

The new breed of synthesized oscillators (Fox's Xpresso and such) do
have internal multi-GHz oscillators locked to a lower frequency rock,
and then synthesize any frequency you want. Jitter in the 12K-20M
range is fs, but I need good jitter down to hundreds of Hz. That's the
hard part. ($1.50 Cardinal XOs have a few ps RMS jitter out to about a
millisecond, then go to hell.) My bang-bang loop may be too slow to
servo out the LF jitter of an Xpresso type XO. It's going to be close.
That's why increasing the PD sample rate, by 5x or 10x maybe, could
make it work.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Bill Sloman]

On Monday, 29 September 2014 10:57:24 UTC+10, dagmarg...@yahoo.com wrote:

Kevin wrote:
dagmargoo...@yahoo.com wrote:
Kevin wrote:

<snip>

The (38.88 x 4) is just one oscillator. It has to be better
than an LC oscillator at 150MHz locked on to its input of 10 MHz.
Any LC variation give direct frequency modulation, which is way,
way worse than a tank drifting a bit. The output frequency of a
tank must still be exactly equal to its input for a fixed change
in component values. A tank oscillator will have a fixed steady
state shift.

Right. I'm not suggesting a 155.52 MHz L-C oscillator! I mean a
155.52 MHz 5th-overtone quartz crystal oscillator, Q>=70k.

You bang the tank and it rings--so far so good. But if the tank isn't
*perfectly* tuned, it rings off frequency, and the 'ring' cycles wander
off phase, right?

Wrong. It isn't the tank that generates the harmonics, but the non-linear response of the multiplying diode. The tank can only respond to the frequencies present in the output of the multiplier. It's essentially a linear part, so can't do any kind of frequency multiplication or inter-modulation on its own.

You do know that tank multiplied oscillators are industry used standard
methods in achieving low phase noise in preference to PLLs?

That's not his crucial element of ignorance - or rather of knowing something that ain't quite so.

No, I didn't, though I believe you.

You'd need a varactor, phase-detector, and a feedback loop to keep the
tank tuned perfectly true, AFAICT, introducing additional problems on
several fronts.

The tank does not have to be perfectly tuned. The tuning doesn't effect the
phase noise. It effects the sub harmonics. For example, tuning at 25 deg C,
then moving to -40 deg, might lose you about 6db from a -50dbc close in
subharmonic.

I'm looking at it in the time domain, and can only imagine you must be
thinking of a different topology than I am.

No, you are not looking at it in the time domain, but rather thinking about it - rather inaccurately - from a time domain perspective.

Run some simulations and see what happens.

Wenzel's topology changes things, since it makes 2f very accurately from a
sine wave, not relying on a tuned tank. Ditto 3f, I *think*.

(Wenzel's odd-multiplier might be an excellent low-noise way to square-up
the 10MHz reference.)

Again, the VCO is in a loop for its close-in stability, e. where temperature
change will produce a transient phase change.

ISTM a custom 155.52 MHz VCXO is literally rock-stable, provides the
best performance attainable, and eliminates a great deal of design
risk and nuisance.

It does not necessarily give the "best" performance. Lower frequency xtals
have much better stability. It might be the "optimum" solution.

By "stability" I assume you mean df/dT, and I'm assuming the whole thing
will have to be ovenized, making that less important.

Thanks for the feedback.

It didn't address your crucial misconception. Kevin probably knows too much about the subject to be able appreciate how you'd got it wrong. I had my nose rubbed in the subject recently, when I was fooling with my low distortion sine-wave oscillator simulations.

--
Bill Sloman, sydney

 

[Gerhard Hoffmann]

Am 28.09.2014 um 18:04 schrieb John Larkin:

The X4 multiplier would have to produce edges that are strictly
periodic to picoseconds. Can that be done?

Seems like you don't use the pointers that I provide.
If it has been done it must be possible.
< http://www.wenzel.com/wp-content/uploads/Sub-pico-Multiplier.pdf >

Wenzel is one of the prime sources in precision oscillators.

CTS does make a surfmount 155.52 fundamental VCXO that claims very low
jitter. Samples are coming, I think.

Check the PN at offset from 0 to 12KHz. It is ignored in the telecom
jitter specs. And that is the interesting part with 1/f.

regards, Gerhard

(too tired for more, after 750 Km Autobahn with abs. max. legally
or technically possible speed..)

 

[Bill Sloman]

On Monday, 29 September 2014 13:25:28 UTC+10, John Larkin wrote:

On Mon, 29 Sep 2014 01:54:37 +0200, Gerhard Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote:
Am 28.09.2014 um 18:04 schrieb John Larkin:

The X4 multiplier would have to produce edges that are strictly
periodic to picoseconds. Can that be done?

Seems like you don't use the pointers that I provide.
If it has been done it must be possible.

http://www.wenzel.com/wp-content/uploads/Sub-pico-Multiplier.pdf

Double oven! Looks like a lot of work.

Really? A couple of Peltier junctions, a couple of thermistors, and a couple of Peltier thermostat chips and you are done. If you want millidegree stability - or better, 20-bit sigma-delta A/D converters on the thermistors and a microprocessor (maybe two) to do the number crunching. It's not rocket science.

Regular ovenised crystals don't use anything as complicated, but a double-oven probably needs a something more ambitious.

Wenzel is one of the prime sources in precision oscillators.

They make an ovenized oscillator with an SC-cut crystal, their ONYX I
series. One version has -100 dB phase noise at 10 Hz out, which is
about 50 dB better than the usual VCXOs. Kvco and pull range are very
low compared to the usual parts, too. It's a sinewave out, but I can
use a fast ecl comparator to square it up.

Obviously. An ECL line receiver would probably be good enough. A comparator typicaly has three stages of gain, while line receivers get by with fewer, so less propagation delay, and less opportunity to get it to oscillate by careless layout.

> That would be a better fit to my bang-bang phase detector.

Or to the kind of phase detector you ought to use - something offering a linear
phase to output voltage characteristic, over +/-6.43nsec of phase at 10MHz.

I've asked
for pricing; 155.52 isn't apparently standard. It would probably be
worth the cost to avoid the engineering of a more exotic loop.

The VXCO is going to define your high-frequency jitter - getting a good VCXO isn't just worth the cost, it pretty much defines the quality that you deliver.

We could use the FPGA to make a frequency counter that could drive a
DAC to tune the VCXO to PPB accuracy against the 10 MHz reference, then
kick in the phase detector.

Why bother switching to an analog system for the fine phase tuning? If you only need 500Hz bandwidth into the voltage control input of the VCXO, a 20-bit (or better) DAC should be fine.

CTS does make a surfmount 155.52 fundamental VCXO that claims very low
jitter. Samples are coming, I think.

Check the PN at offset from 0 to 12KHz. It is ignored in the telecom
jitter specs. And that is the interesting part with 1/f.

The CTS is -50 at 10 Hz, -80 at 100. That's going to be, like, 50 ps
RMS open-loop. Scary.

That's why you are closing the loop at 500Hz.

regards, Gerhard

(too tired for more, after 750 Km Autobahn with abs. max. legally
or technically possible speed..)

Do you have speed limits these days? My Audi is claimed to go 156 MPH,
but I haven't tried it yet.

Some German autobahns were still unrestricted when we last drove
through Germany. We sustained 160 kph over some stretches - roughly
100 mph. The car insurance on stuff that will go faster is quite a
bit more expensive - the insecurities that prompt people to spend
a lot on a flashy car don't make for a cautious driving style.

--
Bill Sloman, Sydney

 

[John Larkin]

On Mon, 29 Sep 2014 01:54:37 +0200, Gerhard Hoffmann
<ghf@hoffmann-hochfrequenz.de> wrote:

Am 28.09.2014 um 18:04 schrieb John Larkin:


The X4 multiplier would have to produce edges that are strictly
periodic to picoseconds. Can that be done?

Seems like you don't use the pointers that I provide.
If it has been done it must be possible.
http://www.wenzel.com/wp-content/uploads/Sub-pico-Multiplier.pdf

Double oven! Looks like a lot of work.

Wenzel is one of the prime sources in precision oscillators.

They make an ovenized oscillator with an SC-cut crystal, their ONYX IV
series. One version has -100 dB phase noise at 10 Hz out, which is
about 50 dB better than the usual VCXOs. Kvco and pull range are very
low compared to the usual parts, too. It's a sinewave out, but I can
use a fast ecl comparator to square it up.

That would be a better fit to my bang-bang phase detector. I've asked
for pricing; 155.52 isn't apparently standard. It would probably be
worth the cost to avoid the engineering of a more exotic loop.

We could use the FPGA to make a frequency counter that could drive a
DAC to tune the XO to PPB accuracy against the 10 MHz reference, then
kick in the phase detector.

CTS does make a surfmount 155.52 fundamental VCXO that claims very low
jitter. Samples are coming, I think.

Check the PN at offset from 0 to 12KHz. It is ignored in the telecom
jitter specs. And that is the interesting part with 1/f.

The CTS is -50 at 10 Hz, -80 at 100. That's going to be, like, 50 ps
RMS open-loop. Scary.

regards, Gerhard

(too tired for more, after 750 Km Autobahn with abs. max. legally
or technically possible speed..)

Do you have speed limits these days? My Audi is claimed to go 156 MPH,
but I haven't tried it yet.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Bill Sloman]

On Monday, 29 September 2014 18:29:12 UTC+10, Gerhard Hoffmann wrote:

Am 29.09.2014 um 06:57 schrieb Bill Sloman:
On Monday, 29 September 2014 13:25:28 UTC+10, John Larkin wrote:

Double oven! Looks like a lot of work.

Really? A couple of Peltier junctions, a couple of thermistors, and a
couple of Peltier thermostat chips and you are done.
If you want millidegree stability - or better -
use 20-bit sigma-delta A/D converters on the thermistors and a
microprocessor (maybe two) to do the number crunching.
It's not rocket science.

Nothing is hard for the man who doesn't have to do it.

I've done it several times, and published one of the better results

Sloman A.W., Buggs P., Molloy J., and Stewart D. "A microcontroller-based driver to stabilise the temperature of an optical stage to 1mK in the range 4C to 38C, using a Peltier heat pump and a thermistor sensor" Measurement Science and Technology, 7 1653-64 (1996) - seventeen citations so far, only two of them by me.

For oven design, see < http://karlquist.com/osc.pdf

_That_ is engineering

They and the team I was involved in seem to have been on the same wavelength. Peltier junctions let you stabilise the crystal at close to room temperature, which does save power, and slows down drift. Not all that cheap, and it does need biggish heat-sinks.

Rick Karlquist is on the timenuts list on febo.com

Some German autobahns were still unrestricted when we last drove
through Germany. We sustained 160 kph over some stretches - roughly
100 mph. The car insurance on stuff that will go faster is quite a
bit more expensive - the insecurities that prompt people to spend
a lot on a flashy car don't make for a cautious driving style.

We have quite good statistics for the Autobahns, in the end that
is what keeps some of them open.

Few people have accidents on autobahns. Flashy cars tend to have more
accidents getting to autobahns and getting from the autobahn exit to
the final destination.

--
Bill Sloman, Sydney

 

[Gerhard Hoffmann]

Am 29.09.2014 um 05:25 schrieb John Larkin:

Do you have speed limits these days? My Audi is claimed to go 156 MPH,
but I haven't tried it yet.

Yes, limits on abt 2/3 of the Autobahn, 120 or 130 Km/h depending on
the state, 50 in towns, 30 in protected areas in town, 100 out of town.
Less depending on local circumstances.
And lots of jam. It's not as much fun as it sounds.

Gerhard

 

[Gerhard Hoffmann]

Am 29.09.2014 um 06:57 schrieb Bill Sloman:

On Monday, 29 September 2014 13:25:28 UTC+10, John Larkin wrote:

Double oven! Looks like a lot of work.

Really? A couple of Peltier junctions, a couple of thermistors, and a couple of Peltier
thermostat chips and you are done. If you want millidegree stability
- or better,
20-bit sigma-delta A/D converters on the thermistors and a
microprocessor (maybe two)
to do the number crunching. It's not rocket science.

Nothing is hard for the man who doesn't have to do it.

For oven design, see < http://karlquist.com/osc.pdf >
_That_ is engineering

Rick Karlquist is on the timenuts list on febo.com

Gerhard

Some German autobahns were still unrestricted when we last drove
through Germany. We sustained 160 kph over some stretches - roughly
100 mph. The car insurance on stuff that will go faster is quite a
bit more expensive - the insecurities that prompt people to spend
a lot on a flashy car don't make for a cautious driving style.

We have quite good statistics for the Autobahns, in the end that
is what keeps some of them open.

 

On Sunday, September 28, 2014 10:21:28 PM UTC-4, Bill Sloman wrote:

On Monday, 29 September 2014 10:57:24 UTC+10, dagmarg...@yahoo.com wrote:
Kevin wrote:
dagmargoo...@yahoo.com wrote:
Kevin wrote:

snip

The (38.88 x 4) is just one oscillator. It has to be better
than an LC oscillator at 150MHz locked on to its input of 10 MHz.
Any LC variation give direct frequency modulation, which is way,
way worse than a tank drifting a bit. The output frequency of a
tank must still be exactly equal to its input for a fixed change
in component values. A tank oscillator will have a fixed steady
state shift.

Right. I'm not suggesting a 155.52 MHz L-C oscillator! I mean a
155.52 MHz 5th-overtone quartz crystal oscillator, Q>=70k.

You bang the tank and it rings--so far so good. But if the tank isn't
*perfectly* tuned, it rings off frequency, and the 'ring' cycles wander
off phase, right?

Wrong. It isn't the tank that generates the harmonics, but the non-linear response of the multiplying diode.

a. Who said anything about a multiplying diode?

b. If you're using an SRD, there's a nearly infinite comb of frequencies in
the output.

> The tank can only respond to the frequencies present in the output of the multiplier. It's essentially a linear part, so can't do any kind of frequency multiplication or inter-modulation on its own.

The tank is typically driven with a rectangular wave or a pulse.
If you ping a tank, it rings at its natural frequency. Period. (So to speak.)

An L-C tank doesn't know or care when the next pulse is coming; you're
implicitly arguing that it does.

You do know that tank multiplied oscillators are industry used standard
methods in achieving low phase noise in preference to PLLs?

That's not his crucial element of ignorance - or rather of knowing something that ain't quite so.

There's a subtlety I'm not familiar with, apparently, that's why I asked,
but I'm very well acquainted with ordinary r.f. frequency multipliers,
since I studied them and invented a new one. We made millions of them.

No, I didn't, though I believe you.

You'd need a varactor, phase-detector, and a feedback loop to keep the
tank tuned perfectly true, AFAICT, introducing additional problems on
several fronts.

The tank does not have to be perfectly tuned. The tuning doesn't effect the
phase noise. It effects the sub harmonics. For example, tuning at 25 deg C,
then moving to -40 deg, might lose you about 6db from a -50dbc close in
subharmonic.

I'm looking at it in the time domain, and can only imagine you must be
thinking of a different topology than I am.

No, you are not looking at it in the time domain, but rather thinking about it - rather inaccurately - from a time domain perspective.

Actually I *am* thinking about it from a time domain perspective, not to
mention lots of real-life on-the-bench actual experience. You know, with
notes and everything.

> Run some simulations and see what happens.

Yes, you ought to.

Version 4
SHEET 1 880 680
WIRE 16 128 -64 128
WIRE 128 128 16 128
WIRE 256 128 192 128
WIRE -64 160 -64 128
WIRE 256 160 256 128
WIRE 336 160 256 160
WIRE 256 240 256 224
WIRE 336 240 256 240
WIRE -64 272 -64 240
WIRE 256 272 256 240
FLAG -64 272 0
FLAG 256 272 0
FLAG 256 128 f_out
FLAG 16 128 input
SYMBOL voltage -64 144 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 20n 20n 500n 2.5u)
SYMBOL diode 128 112 M90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMBOL ind 320 144 R0
SYMATTR InstName L1
SYMATTR Value 20ľH
SYMATTR SpiceLine Rser=.1
SYMBOL cap 240 160 R0
SYMATTR InstName C1
SYMATTR Value 1nF
TEXT -98 296 Left 2 !.tran 20u

Wenzel's topology changes things, since it makes 2f very accurately from a
sine wave, not relying on a tuned tank. Ditto 3f, I *think*.

(Wenzel's odd-multiplier might be an excellent low-noise way to square-up
the 10MHz reference.)

I think this is the crucial difference to typical f_multipliers:
Wenzel's topology makes a clean, essentially perfect squarewave directly
from a pure sine input, rather than ringing a tank to produce / select a
desired harmonic, and there aren't any off-time infinite-spectrum impulses
to excite it.

That's different, and it's pretty cool.

Again, the VCO is in a loop for its close-in stability, e. where temperature
change will produce a transient phase change.

ISTM a custom 155.52 MHz VCXO is literally rock-stable, provides the
best performance attainable, and eliminates a great deal of design
risk and nuisance.

It does not necessarily give the "best" performance. Lower frequency xtals
have much better stability. It might be the "optimum" solution.

By "stability" I assume you mean df/dT, and I'm assuming the whole thing
will have to be ovenized, making that less important.

Thanks for the feedback.

It didn't address your crucial misconception. Kevin probably knows too much about the subject to be able appreciate how you'd got it wrong. I had my nose rubbed in the subject recently, when I was fooling with my low distortion sine-wave oscillator simulations.

Cheers,
James Arthur

 

On Sunday, September 28, 2014 3:16:53 PM UTC-4, Tauno Voipio wrote:

On 28.9.14 19:06, John Larkin wrote:
On Sun, 28 Sep 2014 13:33:50 +0300, Tauno Voipio wrote:
On 28.9.14 11:45, rickman wrote:

In the clock, how do they detect the difference in frequency of the
multiplied VCXO and the Rubidium transition?

The classical method is to sweep the VCXO slightly and observe the
changes in the Rb cell absorption. A servo balances the sweep to
be symmetrical about the sweet point.

IIRC, there was an article about it in an older HP Journal.

https://dl.dropboxusercontent.com/u/53724080/Gear/Efratom.pdf

Thanks John. So the wiggle is done by phase modulation in the
multiplier chain, so the VCXO stays clean.

Interestingly, the phase modulation is only updated at 127Hz.

The VCXO is made with what looks like an old TTL VCO.


Cheers,
James Arthur

 

[ChesterW]

On 9/15/14, 4:55 PM, Phil Hobbs wrote:

On 9/15/2014 5:40 PM, ChesterW wrote:
On 9/14/14, 8:41 PM, Phil Hobbs wrote:
On 9/14/2014 8:56 PM, rickman wrote:
On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First,
the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is
only
being used to isolate the actual clock edges by enabling the
FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John
specifically said that you needed to drive the DFF differentially to
get
the good jitter numbers, so despite having CLK and /CLK pins,
there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output
into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being
divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything
so idiotic.

How would that break the PLL? The reference clock is sampled by
the D
input clocked by the VCXO clock. The divided signal has to be an
enable
on the FF or it won't work because of the inherent delays in
generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in
even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.



*----------------<----------------------------------------*
| |
VCXO *-----* *-----* *-------* |
155.52 MHz ->-- /1944 ->-|D Q|------|D Q|---| LOOP |----*
| | | | | |FILTER |
V *--^--* *--^--* *-------*
| | |
*------->-------* *---<----10MHz REF
Resynch B-B phase det

With maybe a second DFF stage between the phase detector and the loop
filter, to get rid of any noise caused by metastability.

Cheers

Phil Hobbs

It's elegant, but it seems counter-intuitive that the rather tough specs
can be met when throwing away over 99% of the phase comparison
information (1-1/125).

ChesterW

For a constant loop bandwidth, you should get some noise averaging by
doing the phase comparison faster, I agree. However, since you have to
crank down the BW to filter out the gross amounts of ripple from a
bang-bang phase detector, I expect that it won't be that different
inside the BW.

Of course, losing all that loop bandwidth does mean that the VCXO has to
be a lot better than it would with a 10 MHz comparison frequency.

Using local feedback, i.e. a DDS-based or fractional-N loop (wide loop
BW but probably fairly horrible drift) inside an 80-kHz bang-bang loop
would relax the requirements on the VCXO proper.

This is all such fun that I may have to try building something like that.

Cheers

Phil Hobbs

After some thought, I believe that the feedback SNR must improve by
about sqrt as the number of phase comparison measurements increases,
regardless of the loop filter BW, even down to dc. That' about a 10x SNR
increase if all of the phase comparisons are used.

The only scheme I recall using all of the phase comparisons was the two
PLLs in series based on prime factors. That one would increase the base
jitter by sqrt(2) as well as requiring two PLLs though. There may have
been others I missed, this thread is long.

I agree it would be fun to build one of these. Alas, I can't approach
measuring the timing - my fastest is about two orders of magnitude too
slow. Maybe I should have taken your advice about the boat anchor scope
a few weeks back.

ChesterW

 

[ChesterW]

On 9/10/14, 3:29 PM, John Larkin wrote:

On Wed, 10 Sep 2014 14:30:26 -0500, ChesterW <iamsnoozin@yahoo.com
wrote:

On 9/10/14, 9:25 AM, John Larkin wrote:
On Wed, 10 Sep 2014 04:57:02 -0500, ChesterW <iamsnoozin@yahoo.com
wrote:

On 9/9/14, 6:54 PM, John Larkin wrote:


If I hypothetically had a 10 MHz reference and wanted to lock a 155.52
MHz VCXO to it, the obvious way would be to divide both down to 80 KHz
(the GCD) and drive a phase detector back into the VCXO. But that's a
pretty low frequency to run the PD at; to get picosecond stability, an
ordinary analog phase detector would need better than 1 PPM analog
accuracy, which ain't gonna happen.

I can build an ECL edge-sensitive phase detector that might work, but
80K is still pretty low.

There must be tricks to run the phase detector at a higher frequency.

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.



It's clunky, but no tricks required:

increase 10 MHz by 3^4 yielding 810 MHz

Divide 810 MHz by 5^3 yielding 6.48 MHz

increase 6.48 MHz by 2^3 * 3 yielding 155.52 MHz

The prime factors for these odd-sounding frequencies are surprisingly small.

ChesterW

The divisor for 80 KHz mixing are 125 and 1944.

125 = 5 * 5 * 5

1944 = 2 * 2 * 2 * 3 * 3 * 3 * 3 * 3

so there are things that can be done.


Hi John,

Using 80 kHz comes with the requirement for high analog precision. You
wanted to trade speed for precision, a good idea, especially since speed
is so cheap. So you don't care about the prime factors of 80 kHz. The
important factors are:

2^10 * 3^5 * 5^4 = 155.52 MHz and

2^7 * 5^7 = 10 MHz.

One solution to your problem is fractional, which has already been
discussed. To keep the solution in the integers (and above 80 kHz and
below about 20 GHz), I think you need two VCOs and a divider.

The advantage of this approach is that you should have a simple system
with easy-to-predict phase noise and no surprises. The disadvantage is
that you need more parts.

There are combinations other that what I showed earlier, for example you
can increase the 10 MHz by 3^3 yielding 270 MHz. Divide 270 MHz by 5^3
yielding 2.16 MHz. Increase 2.16 MHz by 2^3 * 3^2 yielding 155.52 MHz.

Thanks for the chance to play with the prime numbers. I don't get to do
that often.

ChesterW


Yeah, all sorts of number theory stuff pops up when you do things like
this.


This is sort of interesting: clock a mod-1944 counter from 155.52 MHz.
It ticks every 6.43... ns.

Every 12.5 us, namely every state 0 of the counter, it aligns
perfectly with the 10 MHz ref, whose period is 100 ns.

No other states of the 155 MHz counter align with the 100 ns ref
period, GCD duh, but some come awfully close.

State 902 happens at 5,799.897 ns, which is only 103 ps before a 10
MHz ref edge.

State 1042 is 103 ps late.

State 1244 is 29 ps early.

1493 is 51 ps late.


I wonder if we could work with them somehow.

Intuition and some simple simulation suggests that all of the early/late
phase measurements will sum to zero when the 155.52 MHz is locked to the
10 MHz, and that the sum will increase/decrease monotonically as phase
lock is lost through up/down drift.

If the phase detector is capable of comparing zero crossings differing
by up to a few ns, then you should be able to capture all of the 10 MHz
phase information.

If you can do this, it should buy you about a 20 dB increase in feedback
signal SNR as compared to an 80 kHz phase comparison.

This scheme may need to first lock using 80 kHz phase comparisons, then
switch to the 10 MHz phase comparisons. Both could likely use the same
low BW loop filter though.

ChesterW

 

On Sat, 27 Sep 2014 19:45:17 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/27/2014 4:29 PM, Maynard A. Philbrook Jr. wrote:
In article <m071qv$95b$2@dont-email.me>, gnuarm@gmail.com says...

On 9/27/2014 12:58 PM, DecadentLinuxUserNumeroUno wrote:
On Sat, 27 Sep 2014 08:48:53 -0700 (PDT), Bill Sloman
bill.sloman@gmail.com> Gave us:


Inductance isn't necessarily a problem - within limits.


Yeah... like frequency of operation.

That remark you made about data rates and orders of magnitude can be
assigned to your grasp of the effects of inductance at these data rates
and when trying to generate clean modulation constellations.

Your grasp is DOWN a few orders of magnitude. And a couple decades.

It is always nice to see professionals having a technical conversation.
The mutual respect is obvious.

I've always said this is the place for the after work bar stop.

That wouldn't last long. This crowd would get thrown out of any bar I
would want to frequent. lol

I'm sure you have personal knowledge of this.

 

[Bill Sloman]

On 29/09/2014 11:05 PM, ChesterW wrote:

On 9/15/14, 4:55 PM, Phil Hobbs wrote:
On 9/15/2014 5:40 PM, ChesterW wrote:
On 9/14/14, 8:41 PM, Phil Hobbs wrote:
On 9/14/2014 8:56 PM, rickman wrote:
On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First,
the jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock is not an issue? It is not being used to clock anything. It is
only being used to isolate the actual clock edges by enabling the
FF. It only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John specifically said that you needed to drive the DFF
differentially to get the good jitter numbers, so despite having CLK
and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output
into D and clock it with the undivided signal.

BTW, the FF has to be clocked by the same clock that is being
divided down. Otherwise you get 1 full clock cycle of jitter in the
enable when you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything so idiotic.

How would that break the PLL? The reference clock is sampled by
the D input clocked by the VCXO clock. The divided signal has to be an
enable on the FF or it won't work because of the inherent delays in
generating the divided signal.

Nonsense. It just has to observe the setup and hold times.

If you reclock the divided signal there will be tons of delay in
even an ECL FF.

Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I
think we are not talking about the same circuits.

*----------------<----------------------------------------*
| |
VCXO *-----* *-----* *-------* |
155.52 MHz ->-- /1944 ->-|D Q|------|D Q|---| LOOP |----*
| | | | | |FILTER |
V *--^--* *--^--* *-------*
| | |
*------->-------* *---<----10MHz REF
Resynch B-B phase det

With maybe a second DFF stage between the phase detector and the loop
filter, to get rid of any noise caused by metastability.

It's elegant, but it seems counter-intuitive that the rather tough specs
can be met when throwing away over 99% of the phase comparison
information (1-1/125).

For a constant loop bandwidth, you should get some noise averaging by
doing the phase comparison faster, I agree. However, since you have to
crank down the BW to filter out the gross amounts of ripple from a
bang-bang phase detector, I expect that it won't be that different
inside the BW.

Of course, losing all that loop bandwidth does mean that the VCXO has to
be a lot better than it would with a 10 MHz comparison frequency.

Using local feedback, i.e. a DDS-based or fractional-N loop (wide loop
BW but probably fairly horrible drift) inside an 80-kHz bang-bang loop
would relax the requirements on the VCXO proper.

Neither direct digital synthesis nor fractional-n division would
generate "fairly horrible drift". The DDS includes a DAC to generate the
traditionally stair-case approximation to a 10MHz sine wave derivative
of the 155.52MHz clock - in fact, since this is a fixed frequency
application you could feed it into an integrator to get a straightline
segment approximation to a 10MHz cosine wave.

You have to low-pass either output but essentially only to clean out
155.52MHz components, and either way the DAC/integrator/low pass filter
is only a small a chunk of delay which might drift if you used
temperature sensitive components.

Fractional-n is just a programmable synchronous divider divider,
flipping between dividing by 16 (69 times) and dividing by fifteen (56
times). The phase detector has to cope with up to 6.432nsec of phase
shift between the fractional-n outputs and the 10MHz reference, but
there are no horrible drifting elements before the sampling takes place.

The synchronous counter would be realised in really fast logic, and it's
propagation delay isn't going to more than a nanosecond.

http://www.onsemi.com/pub_link/Collateral/MC10EP016-D.PDF

puts it at 500ps +/-150psec at room temperature rising to
400/560/700psec at 85C.

Not negligible, but small, and difficult to improve on.

This is all such fun that I may have to try building something like that.

After some thought, I believe that the feedback SNR must improve by
about sqrt as the number of phase comparison measurements increases,
regardless of the loop filter BW, even down to dc. That' about a 10x SNR
increase if all of the phase comparisons are used.

The only scheme I recall using all of the phase comparisons was the two
PLLs in series based on prime factors. That one would increase the base
jitter by sqrt(2) as well as requiring two PLLs though. There may have
been others I missed, this thread is long.

Both DDS and fractional-n both offer 125 more comparisons than operating
at 80KHz. If you get cute and operate on both edges of the 10MHz
reference with fractional-n, that becomes 250.

A product phase detector operating on the raw 10MHz reference sine wave
does a whole lot better, and a jittering-around fractional-n derived
switching detector operating on the sine wave only when it was moving up
or down fairly fast might do better still.

I'm thinking about the "synthetic sine wave" the three-level
approximation that has no third harmonic content - zero for 1/6 cycle,
high for 1/3 cycle, zero for 1/6 cycle and low for 1/3 cycle.

Approximating that at 10MHz from a 155.52MHz source would give something
rather ugly, but it would all average out over 1944 cycles of the
155.52MHz clock, or 125 cycles of the 10MHz clock.

I agree it would be fun to build one of these. Alas, I can't approach
measuring the timing - my fastest is about two orders of magnitude too
slow. Maybe I should have taken your advice about the boat anchor scope
a few weeks back.

You can't have too many boat anchor scopes (unless you are living in a
two-bedroom flat in Sydney which doesn't offer storage space for this
kind of luxury - we've now rented the flat next door, but it's taking
time to get it into state that will allow us to start to think about
actually expanding into it).

--
Bill Sloman, Sydney