PLL tricks

[rickman]

On 9/17/2014 3:54 AM, Jan Panteltje wrote:

On a sunny day (Wed, 17 Sep 2014 03:19:11 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lvbclv$8dj$2@dont-email.me>:

On 9/17/2014 3:13 AM, Jan Panteltje wrote:
On a sunny day (Tue, 16 Sep 2014 16:45:59 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lva7in$in1$1@dont-email.me>:


I'm afraid

So what

What the heck is wrong with *you*? I ask you to explain a hand drawn
schematic that I can't understand and you get weird. jeeze

I was hoping to understand what you had done.

Did you not see the words "in parallel" ?
John is right, you really need to pick up some hobby.

Why can't you read and understand my question? Your schematic looks
like the source is connected to the gate. Is that what you intended???
I understand the parallel, but are all the gates supposed to be
connected to all the sources too? Is this a language issue?

--

Rick

 

[Jan Panteltje]

On a sunny day (Wed, 17 Sep 2014 03:57:05 -0400) it happened rickman
<gnuarm@gmail.com> wrote in <lvbet1$moc$2@dont-email.me>:

On 9/17/2014 3:54 AM, Jan Panteltje wrote:
On a sunny day (Wed, 17 Sep 2014 03:19:11 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lvbclv$8dj$2@dont-email.me>:

On 9/17/2014 3:13 AM, Jan Panteltje wrote:
On a sunny day (Tue, 16 Sep 2014 16:45:59 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lva7in$in1$1@dont-email.me>:


I'm afraid

So what

What the heck is wrong with *you*? I ask you to explain a hand drawn
schematic that I can't understand and you get weird. jeeze

I was hoping to understand what you had done.

Did you not see the words "in parallel" ?
John is right, you really need to pick up some hobby.

Why can't you read and understand my question? Your schematic looks
like the source is connected to the gate. Is that what you intended???
I understand the parallel, but are all the gates supposed to be
connected to all the sources too? Is this a language issue?

Yes they are all connected

--

Rick

 

[rickman]

On 9/17/2014 4:06 AM, Jan Panteltje wrote:

On a sunny day (Wed, 17 Sep 2014 03:57:05 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lvbet1$moc$2@dont-email.me>:

On 9/17/2014 3:54 AM, Jan Panteltje wrote:
On a sunny day (Wed, 17 Sep 2014 03:19:11 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lvbclv$8dj$2@dont-email.me>:

On 9/17/2014 3:13 AM, Jan Panteltje wrote:
On a sunny day (Tue, 16 Sep 2014 16:45:59 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lva7in$in1$1@dont-email.me>:


I'm afraid

So what

What the heck is wrong with *you*? I ask you to explain a hand drawn
schematic that I can't understand and you get weird. jeeze

I was hoping to understand what you had done.

Did you not see the words "in parallel" ?
John is right, you really need to pick up some hobby.

Why can't you read and understand my question? Your schematic looks
like the source is connected to the gate. Is that what you intended???
I understand the parallel, but are all the gates supposed to be
connected to all the sources too? Is this a language issue?

Yes they are all connected

My understanding is that when you connect the gate to the source it just
becomes a resistor. What is the FET doing in this circuit?

--

Rick

 

[Jan Panteltje]

On a sunny day (Wed, 17 Sep 2014 04:57:44 -0400) it happened rickman
<gnuarm@gmail.com> wrote in <lvbieo$d77$1@dont-email.me>:

On 9/17/2014 4:06 AM, Jan Panteltje wrote:
On a sunny day (Wed, 17 Sep 2014 03:57:05 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lvbet1$moc$2@dont-email.me>:

On 9/17/2014 3:54 AM, Jan Panteltje wrote:
On a sunny day (Wed, 17 Sep 2014 03:19:11 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lvbclv$8dj$2@dont-email.me>:

On 9/17/2014 3:13 AM, Jan Panteltje wrote:
On a sunny day (Tue, 16 Sep 2014 16:45:59 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lva7in$in1$1@dont-email.me>:


I'm afraid

So what

What the heck is wrong with *you*? I ask you to explain a hand drawn
schematic that I can't understand and you get weird. jeeze

I was hoping to understand what you had done.

Did you not see the words "in parallel" ?
John is right, you really need to pick up some hobby.

Why can't you read and understand my question? Your schematic looks
like the source is connected to the gate. Is that what you intended???
I understand the parallel, but are all the gates supposed to be
connected to all the sources too? Is this a language issue?

Yes they are all connected

My understanding is that when you connect the gate to the source it just
becomes a resistor. What is the FET doing in this circuit?

Decoration

--

Rick

 

[rickman]

On 9/17/2014 5:45 AM, Jan Panteltje wrote:

On a sunny day (Wed, 17 Sep 2014 04:57:44 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lvbieo$d77$1@dont-email.me>:

On 9/17/2014 4:06 AM, Jan Panteltje wrote:
On a sunny day (Wed, 17 Sep 2014 03:57:05 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lvbet1$moc$2@dont-email.me>:

On 9/17/2014 3:54 AM, Jan Panteltje wrote:
On a sunny day (Wed, 17 Sep 2014 03:19:11 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lvbclv$8dj$2@dont-email.me>:

On 9/17/2014 3:13 AM, Jan Panteltje wrote:
On a sunny day (Tue, 16 Sep 2014 16:45:59 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lva7in$in1$1@dont-email.me>:


I'm afraid

So what

What the heck is wrong with *you*? I ask you to explain a hand drawn
schematic that I can't understand and you get weird. jeeze

I was hoping to understand what you had done.

Did you not see the words "in parallel" ?
John is right, you really need to pick up some hobby.

Why can't you read and understand my question? Your schematic looks
like the source is connected to the gate. Is that what you intended???
I understand the parallel, but are all the gates supposed to be
connected to all the sources too? Is this a language issue?

Yes they are all connected

My understanding is that when you connect the gate to the source it just
becomes a resistor. What is the FET doing in this circuit?

Decoration

Ok, thanks for the clear explanation.

--

Rick

 

[Piotr Wyderski]

Jasen Betts wrote:

Absolutely. it's not a counter. it's an accumulator, what you need is
overflow on adding that perform the modulus operation.

It's even not true modulo, just an overflow detector.

However if you've got enough memory for a full wave table (and aren't
using cordic or some other computational method) you could store the
values in the order encountered at your desired step size

A decade ago I developed a sine/cosine calculator for an FPGA-based
quadrature mixer. It was able to run at ~300MHz on the old Cyclone
v. 1.0, far faster than needed -- the ADC was clocked at 65MHz,
the DAC at ~100MHz. It used just one multiplier and a BRAM and
produced results accurate to ~17.3 bits, again far better than needed.

Best regards, Piotr

 

[Kevin Aylward]

"Jan Panteltje" wrote in message news:lvbe40$u1p$1@news.datemas.de...

On a sunny day (Tue, 16 Sep 2014 18:25:52 +0100) it happened "Kevin Aylward"
<ExtractkevinRemove@kevinaylward.co.uk> wrote in
<Q_2dnSi3QYMC74XJnZ2dnUVZ8lKdnZ2d@bt.com>:

So, for example, a 10MHz xtal VCO fed into tanks to multiple up, looks
like
a N*F VCO. This combined HF VCO could be locked in a PLL with your incoming
10MHz, for example.

I would guess that your incoming 10 MHz has a low frequency (< 1Hz) phase
noise way below that which a standard xtal oscillator has. Otherwise, I
still wont understand why 10 mili Hz noise bothers you. Noise ramps up at
30db/dec typically below 100Hz.

Well, yes, multiplying will also multiply any deviation in frequency of
course.

I can say this about LC based UHF VCOs:
I use for example the Firenza vco190-1572t.pdf at 1.5 GHz (GPS frequency):

Frequency Range - 1540 1572 1605 MHz X
Tuning Voltage:

1540 MHz 1 1.4 Vdc X
1605 MHz 3.6 3.9 Vdc X

Tuning Sensitivity - 29 34 39 MHz/V X
Output Power - -3 0 3 dBm X
Output Phase Noise:
10 kHz -106 -100 dBc/Hz
--------------------
100 kHz -128 -122 dBc/Hz X
--------------------

But not so impressive compared to achieving say, -100dBc at 1khz, -130dBc at
10khz, -145dBc at 100kHz,


Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

[John Larkin]

On 16 Sep 2014 10:48:24 GMT, Jasen Betts <jasen@xnet.co.nz> wrote:

On 2014-09-15, Piotr Wyderski <peter.pan@neverland.mil> wrote:
Gerhard Hoffmann wrote:

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

IMHO you don't need to implement the entire counter in BCD.
All you need is a binary counter + a simple compare/reset
circuit to reset the counter after 10e6 steps. The representation
should have no influence on the operating principle. Am I wrong?

Absolutely. it's not a counter. it's an accumulator, what you need is
overflow on adding that perform the modulus operation. I can think of
a coule of different ways to fake that by adding extra "add" steps,
or using different step sizes based on a value comparitor (like the
overflow flag)

However if you've got enough memory for a full wave table (and aren't
using cordic or some other computational method) you could store the
values in the order encountered at your desired step size (if you only
want a single step size) and then, as you propose) use a counter with
a limit reset.

A DDS that resets the counter at some target value is going to have
interesting jitter glitches.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Kevin Aylward]

"Gerhard Hoffmann" wrote in message
news:c7roebFkanlU1@mid.individual.net...

Am 16.09.2014 um 19:25 schrieb Kevin Aylward:

"John Larkin" wrote in message

Won't LC tanks have horrendous temperature coefficients?

Not that bad after all. Assuming a LC Q-factor of 100, you will have a
1 % -3 dB bandwidth. That would allow a 10000 ppm drift across the
temperature range (100 ppm/C across 100 C). After all, you are
interested in the harmonics of the crystal oscillator, not the filter
performance.

Then you need a LC resonance to select the proper overtone of the
crystal. The sweet spot for crystals is at 3-10 MHz,

Actually, its in the range of 10 MHz to 50 MHz for the sweet area over all
constraints of circuit design, xtal design, performance and size for actual
xtal oscillators. That's why the main xtal oscillator venders have lots of
product in that range.

There are a lot of trade offs like aging, power supply sensitivity,
hysteresis, availability of asic processes with the right components, cost
etc.

Not that I am in anyway indicating what I am currently working on, I
entered the thread to make a general discussion point that generating a
high frequency VCO using LC tank multiplication will most likely to
certain, result in much lower phase noise than using a PLL to lock/ that
higher frequency with a HF (low Q) oscillator. i.e. Its difficult to get
a high performance, high stability oscillator directly at say, 2.5 Ghz.
Xtals are shit up there.

There are no crystals up there.

Exactly the point of why one must multiply up.

So, for example, a 10MHz xtal VCO fed into tanks to multiple up, looks
like a N*F VCO. This combined HF VCO could be locked in a PLL with your
incoming 10MHz, for example.

Yes, you can multiply it up, and close to the carrier there will be no
problem. But for every f*10, the noise floor will rise by 20 dB.

I did already make that point in this thread. Its a necessary evil.

And when you have multiplied up to 10 GHz, the carrier will stand
30 dB out of a swamp of noise. Not really attractive.

There is not any realistic alternative, but to multiply up, if you actually
need high frequency references.

Sure, multiplying up from 10 MHz to 10 Ghz is probably not really an
option for low pn. 200Mhz is more realistic. Still tricky with the xtal
oscilater at that frequency, -130 dBc is probably not out of the question
though.

I would guess that your incoming 10 MHz has a low frequency (< 1Hz)
phase noise way below that which a standard xtal oscillator has.

GPS receivers seldom have extra class crystal oscillators. They take
their bragging rights from the long term stability of the airborne,
eeh, vacuum borne Cs clocks.

The point is that, if the discussed system would fail with the phase noise
due to temperature variations of an LC tank filter extracting a clock, then
the system would fail anyway, assuming no errors in my calculations.

I make it:

PN = Q . dKL/dT . KT/W

dKL/dT inductance change with temperature
KT rms amplitude of temperature change, changing sinusoidal at radian
frequency W.

Assuming 1 deg over 1 minute, gets around -95dBc/hz at 1Hz, even faster at 1
deg/sec around -60 dBc/hz phase noise at 1Hz

A typical 10Mhz xtal oscillator will hit maybe -70dBc at 1Hz. A 40Mhz 3rd
overtone, divided down by 4 might hit -90dBc. The point being is that any
phase error of a tank is going to be of the order of what you want get from
a high quality xtal oscillator. So, if a tank wont work, neither will will a
xtal oscillator. Without a xtal oscillator, you're knackered anyway.

For reference, the tank is not being used as the tuning device of an
oscillator. If it were, any shift in L would lead directly to a frequency
shift, which would result in much greater phase noise.

Otherwise, I still wont understand why 10 mili Hz noise bothers you.
Noise ramps up at 30db/dec typically below 100Hz.

I really would like to hear that 30 dB/decade is perfectly normal.
The designer of a very well known low noise op amp found it at least
remarkable (in my battery test results).

I don't understand what you are saying here. All oscillators will,
essentially, have a low frequency noise at 30db/decade. This is because all
devices, have 1/f noise. The LC gives the 20db/decade bit, until it flattens
at very low frequency (Lorentz). There is a sort of exception in principal,
but in realty achieving it is not going to happen in practice. e.g.

http://www.kevinaylward.co.uk/ee/phasenoise/FlickerNoiseNullification.xht

Regarding op amp. It is noted that large audio bipolar transistors are
available with very low 1/f noise. Not so for available HF transistors.

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

[Jan Panteltje]

On a sunny day (Wed, 17 Sep 2014 18:30:53 -0400) it happened rickman
<gnuarm@gmail.com> wrote in <lvd23e$jps$2@dont-email.me>:

Opps, sorry I called it "your" schematic. I got you mixed up with Jan.
So the questions should be for Jan, but I can't seem to get a civil
answer out of him. I guess he has not yet figured out the schematic has
errors. Silly boy.

OK, you are an insulting clueless PIG.
Now to the facts, in KINDERGARTEN kids (at least over here) learn to spell (dog, cat).
later they recognize whole words.
And a bit later they can read a page,
a bit later again they can read a story,
and a bit later grasp the 300 pages novel.

You are STUCK in spelling and endlessy moaning, cannot see the words,
and of course not the diagram and the general meaning of the circuit it represents.
You are an electrodislexic.

PLZ go to electronics.basics.for.dummies.
And on top of that, your analog component knowledge is absent,
JFETS do NOT make resistors with gate and source connected,
look up the datasheet of the BF245, it is a penthode (you do not know about those either)
and flat for voltages > 6 volt.
So piss of, go back to connecting wires to logic gates.
J.L. is right, you are a wste of time.
Do not hold your breath for any replies,
but I would not cry if you did.

 

[rickman]

On 9/18/2014 4:03 AM, Jan Panteltje wrote:

On a sunny day (Wed, 17 Sep 2014 18:30:53 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lvd23e$jps$2@dont-email.me>:

Opps, sorry I called it "your" schematic. I got you mixed up with Jan.
So the questions should be for Jan, but I can't seem to get a civil
answer out of him. I guess he has not yet figured out the schematic has
errors. Silly boy.

OK, you are an insulting clueless PIG.
Now to the facts, in KINDERGARTEN kids (at least over here) learn to spell (dog, cat).
later they recognize whole words.
And a bit later they can read a page,
a bit later again they can read a story,
and a bit later grasp the 300 pages novel.

You are STUCK in spelling and endlessy moaning, cannot see the words,
and of course not the diagram and the general meaning of the circuit it represents.
You are an electrodislexic.

PLZ go to electronics.basics.for.dummies.
And on top of that, your analog component knowledge is absent,
JFETS do NOT make resistors with gate and source connected,
look up the datasheet of the BF245, it is a penthode (you do not know about those either)
and flat for voltages > 6 volt.
So piss of, go back to connecting wires to logic gates.
J.L. is right, you are a wste of time.
Do not hold your breath for any replies,
but I would not cry if you did.

Thank you for your courteous and thoughtful reply.

Do you mean Pentode? You are right, I don't know what a penthode [sic]
is. However I do remember pentodes which are similar to FETs in their
output characteristics. I seem to recall that the bipolar transistor
has similar output characteristics to a triode.

That as it may, looking at the data sheet from NXP

http://www.nxp.com/documents/data_sheet/BF245A-B-C.pdf

Figure 20 shows that with the gate - source voltage at 0 the Rds is
approximately 200 ohms depending on the exact version (A, B, C). Your
circuit shows very low voltages from mV to the voltage needed to drive
the LED. That is not 6 volt and is on the part of the output curve
where the FET is relatively linear given the 0 volt Vgs. So why is that
not a resistor?

The first problem I have in understanding your circuit is just knowing
if I am reading the schematic correctly. Is the circuit such that all
the sources except one are connected to all the gates, connected to the
high voltage, low current side of the transformer. The low voltage and
high current side of the transformer is connected to the one lone
source. Is that correct?

You are right in that I am much more familiar with the digital side of
things. That is why I am asking about your circuit. I would like to
understand how it works. Obviously however the schematic is, it works,
and I'm sure you have good reasons for designing it the way you did.
That is what I'm curious about.

--

Rick

 

[Jasen Betts]

On 2014-09-17, John Larkin <jlarkin@highlandtechnology.com> wrote:

On 16 Sep 2014 10:48:24 GMT, Jasen Betts <jasen@xnet.co.nz> wrote:

On 2014-09-15, Piotr Wyderski <peter.pan@neverland.mil> wrote:
Gerhard Hoffmann wrote:

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

IMHO you don't need to implement the entire counter in BCD.
All you need is a binary counter + a simple compare/reset
circuit to reset the counter after 10e6 steps. The representation
should have no influence on the operating principle. Am I wrong?

Absolutely. it's not a counter. it's an accumulator, what you need is
overflow on adding that perform the modulus operation. I can think of
a coule of different ways to fake that by adding extra "add" steps,
or using different step sizes based on a value comparitor (like the
overflow flag)


However if you've got enough memory for a full wave table (and aren't
using cordic or some other computational method) you could store the
values in the order encountered at your desired step size (if you only
want a single step size) and then, as you propose) use a counter with
a limit reset.

A DDS that resets the counter at some target value is going to have
interesting jitter glitches.

Not if the step size is one and there's a lastch before the DAC output




--
umop apisdn


--- news://freenews.netfront.net/ - complaints: news@netfront.net ---

 

[Piotr Wyderski]

Jasen Betts wrote:

> Not if the step size is one and there's a lastch before the DAC output

Or, if the increments are not of unit size, then a simple conditional
subtractor is enough to handle the overflow. A no-brainer in VHDL.
BCD is not required anywhere in this circuit -- as someone else said,
a number is a number, so chose the simplest(i.e. binary) representation.

Which is an interesting phenomenon on its own. I see exactly the same
behaviour in my professional field: the word "decimal" seems to be
connected to "BCD" by an almost unbreakable mental link. It was a very
enlightening experience to try to persuade an otherwise smart person
that he doesn't need to perform calculations on his fractional number
in BCD just to have decimal arithmetic rules (mostly rounding) and
that the scaled binary integer format can emulate it much more
efficiently. It is a primary-school-level calculus, but the hard part
is to free your adversary from the mental chain of the BCD-related
associations.

Best regards, Piotr

 

[Phil Hobbs]

On 09/18/2014 10:13 AM, Piotr Wyderski wrote:

Jasen Betts wrote:

Not if the step size is one and there's a lastch before the DAC output

Or, if the increments are not of unit size, then a simple conditional
subtractor is enough to handle the overflow. A no-brainer in VHDL.
BCD is not required anywhere in this circuit -- as someone else said,
a number is a number, so chose the simplest(i.e. binary) representation.

Which is an interesting phenomenon on its own. I see exactly the same
behaviour in my professional field: the word "decimal" seems to be
connected to "BCD" by an almost unbreakable mental link. It was a very
enlightening experience to try to persuade an otherwise smart person
that he doesn't need to perform calculations on his fractional number
in BCD just to have decimal arithmetic rules (mostly rounding) and
that the scaled binary integer format can emulate it much more
efficiently. It is a primary-school-level calculus, but the hard part
is to free your adversary from the mental chain of the BCD-related
associations.

Best regards, Piotr

If an N-bit DAC is doing the waveform reconstruction, though, the period
has to be an integer multiple of 2**N clocks. That restricts the range
of choices considerably.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Phil Hobbs]

On 09/18/2014 10:46 AM, Phil Hobbs wrote:

On 09/18/2014 10:13 AM, Piotr Wyderski wrote:
Jasen Betts wrote:

Not if the step size is one and there's a lastch before the DAC
output

Or, if the increments are not of unit size, then a simple
conditional subtractor is enough to handle the overflow. A
no-brainer in VHDL. BCD is not required anywhere in this circuit --
as someone else said, a number is a number, so chose the
simplest(i.e. binary) representation.

Which is an interesting phenomenon on its own. I see exactly the
same behaviour in my professional field: the word "decimal" seems
to be connected to "BCD" by an almost unbreakable mental link. It
was a very enlightening experience to try to persuade an otherwise
smart person that he doesn't need to perform calculations on his
fractional number in BCD just to have decimal arithmetic rules
(mostly rounding) and that the scaled binary integer format can
emulate it much more efficiently. It is a primary-school-level
calculus, but the hard part is to free your adversary from the
mental chain of the BCD-related associations.

Best regards, Piotr



If an N-bit DAC is doing the waveform reconstruction, though, the
period has to be an integer multiple of 2**N clocks. That restricts
the range of choices considerably.

Belay that, shipmates--blow me down for posting before me morning grog.
(Er, coffee. 'Tis Pirate Day along o' the Fiji Isles.)

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Kevin Aylward]

"Gerhard Hoffmann" wrote in message
news:c7umakFd314U1@mid.individual.net...

Am 17.09.2014 um 19:39 schrieb Kevin Aylward:

"Gerhard Hoffmann" wrote in message
news:c7roebFkanlU1@mid.individual.net...


Then you need a LC resonance to select the proper overtone of the
crystal. The sweet spot for crystals is at 3-10 MHz,

Actually, its in the range of 10 MHz to 50 MHz for the sweet area over
all constraints of circuit design, xtal design, performance and size for
actual xtal oscillators. That's why the main xtal oscillator venders
have lots of product in that range.


A typical 10Mhz xtal oscillator will hit maybe -70dBc at 1Hz. A 40Mhz
3rd overtone, divided down by 4 might hit -90dBc.

That proves only that you have a crappy 10 MHz, and a 3/4-crappy 40 MHz
one. The 10811A does -90dBc at 10 MHz/1Hz

Ahmmm....

www.leapsecond.com/museum/10811a/10811a.pd - 72mm X 52mm X 62mm 0.3kg -
30ma, 12V supply

Sure, that will fit into an iPhone

Maybe I have not explained sufficiently. To elaborate:

5mm X 3.2mm X 1.7mm - 4ma, 3V, commercially cost, size, weight, power,
viable to be sold in mass market 100M quantities e.g. sat nav, phones, touch
pads, telecom, is a typical oscillator.



Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

On Friday, September 12, 2014 7:28:21 PM UTC-4, Phil Hobbs wrote:

On 9/12/2014 3:58 PM, dagmargoo...@yahoo.com wrote:
On Friday, September 12, 2014 2:11:10 PM UTC-4, Phil Hobbs wrote:
On 09/11/2014 10:59 PM, dagmargoo...@yahoo.com wrote:
On Thursday, September 11, 2014 8:24:15 PM UTC-4, John Larkin wrote:

Equations seldom design stuff.

Yep. Equations usually describe stuff someone already did, help
others duplicate, and sometimes refine it.

That's unduly pessimistic. Before designing an instrument, I always
calculate how good it _could_ be, from first principles where possible.

That way I can (a) select the best possible approach, and (b) know when
it isn't there yet. I couldn't do my job without crunching a fair bit
of math. My rule of thumb is that the final result gets within 1 dB of
the theory most of the time, and within 3 dB almost always (i.e. unless
I've made a math blunder or failed to think of some physical effect that
turns out to be important).

Granted, in your situation.

More often I'm trying to solve novel problems. A long time ago, it was
making clean BPSK SS UHF cheaply from a cheap crystal, at micropower,
fast-settling, with a lot of other constraints. There simply isn't an
equation that outputs a novel topology.

Quite so. OTOH calculating the fundamental limits as a function of the
crystal Q and transistor noise can be pretty illuminating. A few years
ago when I was building stabilized lasers for downhole applications, I
had to go into a lot of that stuff, and learned a lot. (Leeson's
equation for oscillator noise is sort of the electronic analogue of the
Schawlow-Townes minimum line width of a laser.)

If you can't calculate how good it _could_ be, how do you know when
you're done?

Right, but that's usually a later stage, isn't it?

To answer more directly, here's my process here--we already know (I think)
that oscillator phase performance is limited by resonator Q and flicker
noise in the BJT, and that crystals have the highest Q available in this
frequency range.

Robert J. Matthys wrote extensively about VHF crystal oscillator design
in RF Design in two articles in the '80s. (buried in my dungeon somewhere)
IIRC, the jist of it was that very, very high performance was attainable
at VHF using over-tone crystals, the trick being not to spoil the
crystal's inherent Q, which most people do.

So, as a first approximation, we 'know' the lowest phase-noise solution is
likely to involve a quartz crystal and the best transistor we can find.

We also know that multiplying up x1944 from 80KHz--essentially John's
problem--is a mother (of invention), and that a lower multiplier would
help a great deal on several fronts.

All of that qualitative logic led me to propose:

Reference Generator Master Oscillator
.------------------------------. .------------------------.
| VCXO | 720 | VCXO |
| .---. .---. .---. .----. | KHz | .---. .---. .---. |
10MHz >---| x |->|LPF|->| ~ |-+-|/125|--------->| X |->|LPF|->| ~ |-+---> 155.52MHz
| '---' '---' '---' | '----' | | '---' '---' '---' | |
| ^ 90 MHz | | | ^ .------. | |
| '-----------------' | | '----| /216 |-----' |
'------------------------------' | '------' |
'-----------------------'

The reference generator's phase detector runs at 10MHz and its VCXO
output is at least as good as the Master Oscillator's VCXO, so this
block doesn't, to a first order, limit performance.

I believe it's a lot better than Kevin's passive multiplier because the
crystal is so much better than any other [passive selection filter +
amplifier] scheme. I think. Maybe Kevin will correct me.

So that's my typical stream-of-consciousness, birthed whilst jogging.

The next step is usually "Dang--fatal flaw--that won't work because..."

Computations come next, e.g., "Am I getting the theoretical performance
from this crystal with this magnificent Q?"

If that weren't good enough I might also look at other high-factor
multiplier topologies (such as those used for microwave sources) and
evaluate them.

It's a pity to declare victory and leave, when there's
another 20 dB available with affordable devices. (Yes, I know about
engineering being the art of "good enough for the lowest cost", but
better performance is always worth something--you can trade it for a
higher selling price, wider spec limits, and/or a quieter life.)

More recently I was tasked loading a device with a ~500A max inrush onto
a supply made to trip-out around a tenth of that, with everything COTS
and "untouchable," lest the certifications be spoiled. That too was
solved with a novel external topology, custom for the application.

Put a penny into the fusebox, Ralph.

That's kind of what I did! (I made a constant-current SMPS that pre-charged
the load's 0.1F input cap., then dropped a 500A short-protected MOSFET
'penny' into the 'fusebox.')

Cheers,
James Arthur

 

On Friday, September 12, 2014 9:18:41 PM UTC-4, mrob...@att.net wrote:

Jan Panteltje wrote:

You do not, as bird, use take off weight, calculate needed runway
length, get weather report, fuel..., vectors, you just flap the wings
and go.

Sort of related: European starlings (Sturnus vulgaris) develop about
10 to 15 W of metabolic power, and deliver about 1 to 2.5 W at the
wings. I hadn't thought about it much before I read the paper, but I
was suprised at how small those numbers are. It's almost like the
design has been iterated for millions of years, or something.

(Reference: http://jeb.biologists.org/content/204/19/3311 )

Pretty neat that a 100g critter makes 15W. Also neat that going from
23Km/hr to 52Km/hr only increases draw from 10.4 to 14.9W.

Now if we only had those figures for other species, we could compute the
air speed velocity of a laden swallow. ("African or European swallow,"
you ask...)

Cheers,
James Arthur

 

[Lasse Langwadt Christense]

Den fredag den 19. september 2014 16.11.10 UTC+2 skrev dagmarg...@yahoo.com:

On Friday, September 12, 2014 9:18:41 PM UTC-4, mrob...@att.net wrote:

Jan Panteltje wrote:



You do not, as bird, use take off weight, calculate needed runway

length, get weather report, fuel..., vectors, you just flap the wings

and go.



Sort of related: European starlings (Sturnus vulgaris) develop about

10 to 15 W of metabolic power, and deliver about 1 to 2.5 W at the

wings. I hadn't thought about it much before I read the paper, but I

was suprised at how small those numbers are. It's almost like the

design has been iterated for millions of years, or something.



(Reference: http://jeb.biologists.org/content/204/19/3311 )



Pretty neat that a 100g critter makes 15W. Also neat that going from

23Km/hr to 52Km/hr only increases draw from 10.4 to 14.9W.

the Tour de France riders put around 6W/kg in the pedals all day, in
the sprint the best can do around 22W/kg for a few seconds


-Lasse

 

On Friday, September 19, 2014 11:01:36 AM UTC-4, Bill Sloman wrote:

On 20/09/2014 12:11 AM, dagmargoo...@yahoo.com wrote:
On Friday, September 12, 2014 9:18:41 PM UTC-4, mrob...@att.net wrote:
Jan Panteltje wrote:

You do not, as bird, use take off weight, calculate needed runway
length, get weather report, fuel..., vectors, you just flap the wings
and go.

Sort of related: European starlings (Sturnus vulgaris) develop about
10 to 15 W of metabolic power, and deliver about 1 to 2.5 W at the
wings. I hadn't thought about it much before I read the paper, but I
was suprised at how small those numbers are. It's almost like the
design has been iterated for millions of years, or something.

(Reference: http://jeb.biologists.org/content/204/19/3311 )

Pretty neat that a 100g critter makes 15W. Also neat that going from
23Km/hr to 52Km/hr only increases draw from 10.4 to 14.9W.

Now if we only had those figures for other species, we could compute the
air speed velocity of a laden swallow. ("African or European swallow,"
you ask...)

Actually, I'm more puzzled about what an "air speed velocity" might be.

"Air speed" is a familiar term, and "flight velocity" might be one
that a physicist might use, but the mixed term sounds odd.

https://www.youtube.com/watch?gl=IL&hl=en&v=9JJPBVwc1iM

Cheers,
James Arthur