PLL tricks

[Phil Hobbs]

On 9/16/2014 3:19 PM, rickman wrote:

On 9/16/2014 2:39 PM, Phil Hobbs wrote:
On 09/16/2014 12:27 PM, rickman wrote:
On 9/16/2014 8:19 AM, Phil Hobbs wrote:
On 9/16/2014 12:31 AM, rickman wrote:
On 9/15/2014 11:08 PM, John Larkin wrote:
On Mon, 15 Sep 2014 22:37:19 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/15/2014 10:33 PM, John Larkin wrote:
On Mon, 15 Sep 2014 22:18:05 -0400, rickman <gnuarm@gmail.com
wrote:

That is RMS, I was quoting peak (max). See above in the text you
quoted...

The RMS jitter is specified as 200 fs typ, and the RMS jitter is
specified as 1 ps RMS max.

Ok, so just the two FFs in your circuit create 1.4 ps of jitter RMS
"max" then, no?

No. They are inside the PLL feedback loop.

You might consider moving over to the "basics" newsgroup. It gets
timesome explaining this simple of stuff to newbies.

I know, it is hard to explain something you don't understand.

How can a very slow PLL reduce the cycle to cycle jitter of the PD?


The jitter has some (very wide) intrinsic frequency spectrum, which
will
get folded (aliased) a zillion times into the fundamental interval, and
will therefore be very nearly white, apart from possible power supply
problems.

The loop bandwidth will probably be only a few hundred hertz, because
you have to filter out the gross ugly ripple from the bang-bang PD
without making the loop unstable. Say 200 clocks at 80 kHz.

Most of the DFF's jitter will thus get filtered out.

That isn't the question. He is looking to make a PD with 1 ps jitter.
He is using two FFs with RMS jitter of 1 ps each yielding 1.4 ps of RMA
jitter. How does the filter change this spec?


You're not thinking very hard, or have forgotten how to go from time to
frequency and back.

Jitter is proportional to phase noise in radians for small excursions

White phase noise -> RMS phase error proportional to sqrt(BW)

BW is 0.5% of rep rate -> sqrt(BW) = 7% of full interval -> max RMS
jitter is ~ 7% of 1.4 ps ~= 0.1 ps.

That isn't the PD. He said he wanted a PD with 1 ps of jitter. He has
a PD with 1.4 ps of jitter... I'm just sayin'


Way to move the goal posts, guy. You're just blowing smoke at this point.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[rickman]

On 9/16/2014 5:20 PM, Phil Hobbs wrote:

On 9/16/2014 3:19 PM, rickman wrote:
On 9/16/2014 2:39 PM, Phil Hobbs wrote:
On 09/16/2014 12:27 PM, rickman wrote:
On 9/16/2014 8:19 AM, Phil Hobbs wrote:
On 9/16/2014 12:31 AM, rickman wrote:
On 9/15/2014 11:08 PM, John Larkin wrote:
On Mon, 15 Sep 2014 22:37:19 -0400, rickman <gnuarm@gmail.com
wrote:

On 9/15/2014 10:33 PM, John Larkin wrote:
On Mon, 15 Sep 2014 22:18:05 -0400, rickman <gnuarm@gmail.com
wrote:

That is RMS, I was quoting peak (max). See above in the text you
quoted...

The RMS jitter is specified as 200 fs typ, and the RMS jitter is
specified as 1 ps RMS max.

Ok, so just the two FFs in your circuit create 1.4 ps of jitter RMS
"max" then, no?

No. They are inside the PLL feedback loop.

You might consider moving over to the "basics" newsgroup. It gets
timesome explaining this simple of stuff to newbies.

I know, it is hard to explain something you don't understand.

How can a very slow PLL reduce the cycle to cycle jitter of the PD?


The jitter has some (very wide) intrinsic frequency spectrum, which
will
get folded (aliased) a zillion times into the fundamental interval,
and
will therefore be very nearly white, apart from possible power supply
problems.

The loop bandwidth will probably be only a few hundred hertz, because
you have to filter out the gross ugly ripple from the bang-bang PD
without making the loop unstable. Say 200 clocks at 80 kHz.

Most of the DFF's jitter will thus get filtered out.

That isn't the question. He is looking to make a PD with 1 ps jitter.
He is using two FFs with RMS jitter of 1 ps each yielding 1.4 ps of RMA
jitter. How does the filter change this spec?


You're not thinking very hard, or have forgotten how to go from time to
frequency and back.

Jitter is proportional to phase noise in radians for small excursions

White phase noise -> RMS phase error proportional to sqrt(BW)

BW is 0.5% of rep rate -> sqrt(BW) = 7% of full interval -> max RMS
jitter is ~ 7% of 1.4 ps ~= 0.1 ps.

That isn't the PD. He said he wanted a PD with 1 ps of jitter. He has
a PD with 1.4 ps of jitter... I'm just sayin'


Way to move the goal posts, guy. You're just blowing smoke at this point.

No, those *are* the goal posts. Otherwise why use the ECL at all?

--

Rick

 

[Gerhard Hoffmann]

Am 16.09.2014 um 19:25 schrieb Kevin Aylward:

"John Larkin" wrote in message

Won't LC tanks have horrendous temperature coefficients?

Not that bad after all. Assuming a LC Q-factor of 100, you will have a
1 % -3 dB bandwidth. That would allow a 10000 ppm drift across the
temperature range (100 ppm/C across 100 C). After all, you are
interested in the harmonics of the crystal oscillator, not the filter
performance.

A working Q of 100 is way too much.

The filter performance is important. For one, you have the
varicap/inductor series resonance that is in series to the crystal.
It is needed to implement the tuning voltage input.

Then you need a LC resonance to select the proper overtone of the
crystal. The sweet spot for crystals is at 3-10 MHz, and even 10 MHz
crystal ovens often contain overtone crystals with the fundamental
at 3.333 MHz. At 100 MHz there are no alternatives to overtones.

Those extra thin etched inverted mesa crystals often mentioned here
are completely fragile and have ridiculous Q.
Close to the carrier, Q is the only thing that counts wrt phase noise.

SC cut crystals also have an additional resonance 14% higher than
their intended series frequency and that must be suppressed.

And C0, the capacitance of the holder and the crystal seen as
just two plates with something in between, piezo effect ignored,
must be compensated with a parallel coil at >= 50 MHz.
You never get a real valued series resonance otherwise.

So, there are always a lot of inductor resonances involved in
a quality crystal oscillator.

Enrico Rubiola describes in his book how the size of an object
has influence on its phase noise. That can be seen in microwave
transistors (faster = smaller = more 1/f noise, fight back with
paralleling) or in crystals (faster = smaller = more noise, fight
back with overtones), and my 20 parallel op amps belong to this
area also.

Rubiola is required reading. http://rubiola.org

Not that I am in anyway indicating what I am currently working on, I
entered the thread to make a general discussion point that generating a
high frequency VCO using LC tank multiplication will most likely to
certain, result in much lower phase noise than using a PLL to lock/ that
higher frequency with a HF (low Q) oscillator. i.e. Its difficult to get
a high performance, high stability oscillator directly at say, 2.5 Ghz.
Xtals are shit up there.

There are no crystals up there. Whispering gallery mode saphires, maybe.
And the product of f and Q in crystals is constant.

,

So, for example, a 10MHz xtal VCO fed into tanks to multiple up, looks
like a N*F VCO. This combined HF VCO could be locked in a PLL with your
incoming 10MHz, for example.

Yes, you can multiply it up, and close to the carrier there will be no
problem. But for every f*10, the noise floor will rise by 20 dB.
And when you have multiplied up to 10 GHz, the carrier will stand
30 dB out of a swamp of noise. Not really attractive.

You can have filters in an intermediate stage like in the HP8662A
that has crystal filters at 160 MHz and SAWs at 640 MHz in its
reference chain.

Or you can build an xtal oscillator at 100 MHz, use its low noise
floor and lock it to a 10 MHz reference that is really clean close
to the carrier, so you get the best of both worlds.

I would guess that your incoming 10 MHz has a low frequency (< 1Hz)
phase noise way below that which a standard xtal oscillator has.

GPS receivers seldom have extra class crystal oscillators. They take
their bragging rights from the long term stability of the airborne,
eeh, vacuum borne Cs clocks.

Otherwise, I still wont understand why 10 mili Hz noise bothers you.
Noise ramps up at 30db/dec typically below 100Hz.

I really would like to hear that 30 dB/decade is perfectly normal.
The designer of a very well known low noise op amp found it at least
remarkable (in my battery test results).

regards, Gerhard

 

[Phil Hobbs]

On 9/16/2014 5:28 PM, rickman wrote:

On 9/16/2014 5:20 PM, Phil Hobbs wrote:
On 9/16/2014 3:19 PM, rickman wrote:
On 9/16/2014 2:39 PM, Phil Hobbs wrote:
On 09/16/2014 12:27 PM, rickman wrote:
On 9/16/2014 8:19 AM, Phil Hobbs wrote:
On 9/16/2014 12:31 AM, rickman wrote:
On 9/15/2014 11:08 PM, John Larkin wrote:
On Mon, 15 Sep 2014 22:37:19 -0400, rickman <gnuarm@gmail.com
wrote:

On 9/15/2014 10:33 PM, John Larkin wrote:
On Mon, 15 Sep 2014 22:18:05 -0400, rickman <gnuarm@gmail.com
wrote:

That is RMS, I was quoting peak (max). See above in the text
you
quoted...

The RMS jitter is specified as 200 fs typ, and the RMS jitter is
specified as 1 ps RMS max.

Ok, so just the two FFs in your circuit create 1.4 ps of jitter
RMS
"max" then, no?

No. They are inside the PLL feedback loop.

You might consider moving over to the "basics" newsgroup. It gets
timesome explaining this simple of stuff to newbies.

I know, it is hard to explain something you don't understand.

How can a very slow PLL reduce the cycle to cycle jitter of the PD?


The jitter has some (very wide) intrinsic frequency spectrum, which
will
get folded (aliased) a zillion times into the fundamental interval,
and
will therefore be very nearly white, apart from possible power supply
problems.

The loop bandwidth will probably be only a few hundred hertz, because
you have to filter out the gross ugly ripple from the bang-bang PD
without making the loop unstable. Say 200 clocks at 80 kHz.

Most of the DFF's jitter will thus get filtered out.

That isn't the question. He is looking to make a PD with 1 ps jitter.
He is using two FFs with RMS jitter of 1 ps each yielding 1.4 ps of
RMA
jitter. How does the filter change this spec?


You're not thinking very hard, or have forgotten how to go from time to
frequency and back.

Jitter is proportional to phase noise in radians for small excursions

White phase noise -> RMS phase error proportional to sqrt(BW)

BW is 0.5% of rep rate -> sqrt(BW) = 7% of full interval -> max RMS
jitter is ~ 7% of 1.4 ps ~= 0.1 ps.

That isn't the PD. He said he wanted a PD with 1 ps of jitter. He has
a PD with 1.4 ps of jitter... I'm just sayin'


Way to move the goal posts, guy. You're just blowing smoke at this
point.

No, those *are* the goal posts. Otherwise why use the ECL at all?

You're just being thick then. Try plugging those numbers John gave for
the FPGA into the same math I just went through. Doesn't give the same
results at all, and in addition there's the huge drift.

It's the VCXO output that matters.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[rickman]

On 9/16/2014 5:43 PM, Phil Hobbs wrote:

On 9/16/2014 5:28 PM, rickman wrote:
On 9/16/2014 5:20 PM, Phil Hobbs wrote:
On 9/16/2014 3:19 PM, rickman wrote:
On 9/16/2014 2:39 PM, Phil Hobbs wrote:
On 09/16/2014 12:27 PM, rickman wrote:
On 9/16/2014 8:19 AM, Phil Hobbs wrote:
On 9/16/2014 12:31 AM, rickman wrote:
On 9/15/2014 11:08 PM, John Larkin wrote:
On Mon, 15 Sep 2014 22:37:19 -0400, rickman <gnuarm@gmail.com
wrote:

On 9/15/2014 10:33 PM, John Larkin wrote:
On Mon, 15 Sep 2014 22:18:05 -0400, rickman <gnuarm@gmail.com
wrote:

That is RMS, I was quoting peak (max). See above in the text
you
quoted...

The RMS jitter is specified as 200 fs typ, and the RMS jitter is
specified as 1 ps RMS max.

Ok, so just the two FFs in your circuit create 1.4 ps of jitter
RMS
"max" then, no?

No. They are inside the PLL feedback loop.

You might consider moving over to the "basics" newsgroup. It gets
timesome explaining this simple of stuff to newbies.

I know, it is hard to explain something you don't understand.

How can a very slow PLL reduce the cycle to cycle jitter of the PD?


The jitter has some (very wide) intrinsic frequency spectrum, which
will
get folded (aliased) a zillion times into the fundamental interval,
and
will therefore be very nearly white, apart from possible power
supply
problems.

The loop bandwidth will probably be only a few hundred hertz,
because
you have to filter out the gross ugly ripple from the bang-bang PD
without making the loop unstable. Say 200 clocks at 80 kHz.

Most of the DFF's jitter will thus get filtered out.

That isn't the question. He is looking to make a PD with 1 ps
jitter.
He is using two FFs with RMS jitter of 1 ps each yielding 1.4 ps of
RMA
jitter. How does the filter change this spec?


You're not thinking very hard, or have forgotten how to go from
time to
frequency and back.

Jitter is proportional to phase noise in radians for small excursions

White phase noise -> RMS phase error proportional to sqrt(BW)

BW is 0.5% of rep rate -> sqrt(BW) = 7% of full interval -> max RMS
jitter is ~ 7% of 1.4 ps ~= 0.1 ps.

That isn't the PD. He said he wanted a PD with 1 ps of jitter. He has
a PD with 1.4 ps of jitter... I'm just sayin'


Way to move the goal posts, guy. You're just blowing smoke at this
point.

No, those *are* the goal posts. Otherwise why use the ECL at all?


You're just being thick then. Try plugging those numbers John gave for
the FPGA into the same math I just went through. Doesn't give the same
results at all, and in addition there's the huge drift.

It's the VCXO output that matters.

Of course it is the VCXO output that matters. I'm just showing that the
spec John gave was 1 ps jitter on the PD which is not what he is getting.

--

Rick

 

[Phil Hobbs]

On 9/16/2014 6:08 PM, rickman wrote:

On 9/16/2014 5:43 PM, Phil Hobbs wrote:
On 9/16/2014 5:28 PM, rickman wrote:
On 9/16/2014 5:20 PM, Phil Hobbs wrote:
On 9/16/2014 3:19 PM, rickman wrote:
On 9/16/2014 2:39 PM, Phil Hobbs wrote:
On 09/16/2014 12:27 PM, rickman wrote:
On 9/16/2014 8:19 AM, Phil Hobbs wrote:
On 9/16/2014 12:31 AM, rickman wrote:
On 9/15/2014 11:08 PM, John Larkin wrote:
On Mon, 15 Sep 2014 22:37:19 -0400, rickman <gnuarm@gmail.com
wrote:

On 9/15/2014 10:33 PM, John Larkin wrote:
On Mon, 15 Sep 2014 22:18:05 -0400, rickman <gnuarm@gmail.com
wrote:

That is RMS, I was quoting peak (max). See above in the text
you
quoted...

The RMS jitter is specified as 200 fs typ, and the RMS
jitter is
specified as 1 ps RMS max.

Ok, so just the two FFs in your circuit create 1.4 ps of jitter
RMS
"max" then, no?

No. They are inside the PLL feedback loop.

You might consider moving over to the "basics" newsgroup. It gets
timesome explaining this simple of stuff to newbies.

I know, it is hard to explain something you don't understand.

How can a very slow PLL reduce the cycle to cycle jitter of the
PD?


The jitter has some (very wide) intrinsic frequency spectrum, which
will
get folded (aliased) a zillion times into the fundamental interval,
and
will therefore be very nearly white, apart from possible power
supply
problems.

The loop bandwidth will probably be only a few hundred hertz,
because
you have to filter out the gross ugly ripple from the bang-bang PD
without making the loop unstable. Say 200 clocks at 80 kHz.

Most of the DFF's jitter will thus get filtered out.

That isn't the question. He is looking to make a PD with 1 ps
jitter.
He is using two FFs with RMS jitter of 1 ps each yielding 1.4 ps of
RMA
jitter. How does the filter change this spec?


You're not thinking very hard, or have forgotten how to go from
time to
frequency and back.

Jitter is proportional to phase noise in radians for small excursions

White phase noise -> RMS phase error proportional to sqrt(BW)

BW is 0.5% of rep rate -> sqrt(BW) = 7% of full interval -> max RMS
jitter is ~ 7% of 1.4 ps ~= 0.1 ps.

That isn't the PD. He said he wanted a PD with 1 ps of jitter. He
has
a PD with 1.4 ps of jitter... I'm just sayin'


Way to move the goal posts, guy. You're just blowing smoke at this
point.

No, those *are* the goal posts. Otherwise why use the ECL at all?


You're just being thick then. Try plugging those numbers John gave for
the FPGA into the same math I just went through. Doesn't give the same
results at all, and in addition there's the huge drift.

It's the VCXO output that matters.

Of course it is the VCXO output that matters. I'm just showing that the
spec John gave was 1 ps jitter on the PD which is not what he is getting.

Honestly, Rick, is chewing on people's ankles like this the most
interesting thing you can find to do?

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Maynard A. Philbrook Jr.]

In article <lva7n7$in1$2@dont-email.me>, gnuarm@gmail.com says...

On 9/16/2014 4:45 PM, rickman wrote:
On 9/16/2014 4:52 AM, Jan Panteltje wrote:
On a sunny day (Tue, 16 Sep 2014 00:39:45 +0200) it happened Gerhard
Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote in
c7p85hF8ojU1@mid.individual.net>:


On 9/15/2014 2:40 PM, Jan Panteltje wrote:

I think this is nice:
http://www.arrl.org/files/file/Technology/ard/rohde94.pdf
I always use JFET oscillators.

I almost never do. Bipolars are much more predictable.

That is is true,
but even then I found these JFET oscilators are very stable and noise
free.
You can use those in parallel too:
http://panteltje.com/pub/lighting_a_LED_with_a_candle_IMG_3604.GIF
Not exactly a 'low noise' application,
but for sure a 'low voltage application'.

http://panteltje.com/pub/lighting_a_LED_with_a_candle_setup_IMG_3607.GIF

I'm afraid I can't read your schematic. How are the FETs connected to
the transformer? It looks like all the gates, all the drains and the
two coils of the transformer are all shorted together.

Opps, make that all the gates and all the sources...

And what's the problem with that?

Jamie

 

[John Larkin]

On Tue, 16 Sep 2014 18:45:59 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 9/16/2014 6:08 PM, rickman wrote:
On 9/16/2014 5:43 PM, Phil Hobbs wrote:
On 9/16/2014 5:28 PM, rickman wrote:
On 9/16/2014 5:20 PM, Phil Hobbs wrote:
On 9/16/2014 3:19 PM, rickman wrote:
On 9/16/2014 2:39 PM, Phil Hobbs wrote:
On 09/16/2014 12:27 PM, rickman wrote:
On 9/16/2014 8:19 AM, Phil Hobbs wrote:
On 9/16/2014 12:31 AM, rickman wrote:
On 9/15/2014 11:08 PM, John Larkin wrote:
On Mon, 15 Sep 2014 22:37:19 -0400, rickman <gnuarm@gmail.com
wrote:

On 9/15/2014 10:33 PM, John Larkin wrote:
On Mon, 15 Sep 2014 22:18:05 -0400, rickman <gnuarm@gmail.com
wrote:

That is RMS, I was quoting peak (max). See above in the text
you
quoted...

The RMS jitter is specified as 200 fs typ, and the RMS
jitter is
specified as 1 ps RMS max.

Ok, so just the two FFs in your circuit create 1.4 ps of jitter
RMS
"max" then, no?

No. They are inside the PLL feedback loop.

You might consider moving over to the "basics" newsgroup. It gets
timesome explaining this simple of stuff to newbies.

I know, it is hard to explain something you don't understand.

How can a very slow PLL reduce the cycle to cycle jitter of the
PD?


The jitter has some (very wide) intrinsic frequency spectrum, which
will
get folded (aliased) a zillion times into the fundamental interval,
and
will therefore be very nearly white, apart from possible power
supply
problems.

The loop bandwidth will probably be only a few hundred hertz,
because
you have to filter out the gross ugly ripple from the bang-bang PD
without making the loop unstable. Say 200 clocks at 80 kHz.

Most of the DFF's jitter will thus get filtered out.

That isn't the question. He is looking to make a PD with 1 ps
jitter.
He is using two FFs with RMS jitter of 1 ps each yielding 1.4 ps of
RMA
jitter. How does the filter change this spec?


You're not thinking very hard, or have forgotten how to go from
time to
frequency and back.

Jitter is proportional to phase noise in radians for small excursions

White phase noise -> RMS phase error proportional to sqrt(BW)

BW is 0.5% of rep rate -> sqrt(BW) = 7% of full interval -> max RMS
jitter is ~ 7% of 1.4 ps ~= 0.1 ps.

That isn't the PD. He said he wanted a PD with 1 ps of jitter. He
has
a PD with 1.4 ps of jitter... I'm just sayin'


Way to move the goal posts, guy. You're just blowing smoke at this
point.

No, those *are* the goal posts. Otherwise why use the ECL at all?


You're just being thick then. Try plugging those numbers John gave for
the FPGA into the same math I just went through. Doesn't give the same
results at all, and in addition there's the huge drift.

It's the VCXO output that matters.

Of course it is the VCXO output that matters. I'm just showing that the
spec John gave was 1 ps jitter on the PD which is not what he is getting.


Honestly, Rick, is chewing on people's ankles like this the most
interesting thing you can find to do?

Cheers

Phil Hobbs

Maybe I should wash my sox more often.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[John Larkin]

On Tue, 16 Sep 2014 15:25:36 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/15/2014 7:03 PM, Bill Sloman wrote:
On Tuesday, 16 September 2014 00:26:02 UTC+10, Piotr Wyderski wrote:
Gerhard Hoffmann wrote:

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

IMHO you don't need to implement the entire counter in BCD.
All you need is a binary counter + a simple compare/reset
circuit to reset the counter after 10e6 steps. The representation
should have no influence on the operating principle. Am I wrong?

I don't think so. I think the point that was being made was that most DDS chips have a fixed binary modulus or 2^32 or 2^48 or whatever, so that you can't get an exact frequency match to any number that isn't a power of two.

I'd be willing to bet that most DDS chips are FPGAs or CPUs where you
can do whatever you like.

We usually do DDS sources in an FPGA, with just an external DAC.
That's much cheaper and easier to interface than a bought DDS chip.

We have an upcoming project where we plan to use a little ARM CPU,
LPC1768, to do software DDS into its own 10-bit DAC, to generate sine
waves around 400 Hz. That should be fun.





--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[josephkk]

On Tue, 16 Sep 2014 15:25:36 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/15/2014 7:03 PM, Bill Sloman wrote:
On Tuesday, 16 September 2014 00:26:02 UTC+10, Piotr Wyderski wrote:
Gerhard Hoffmann wrote:

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

IMHO you don't need to implement the entire counter in BCD.
All you need is a binary counter + a simple compare/reset
circuit to reset the counter after 10e6 steps. The representation
should have no influence on the operating principle. Am I wrong?

I don't think so. I think the point that was being made was that most DDS chips have a fixed binary modulus or 2^32 or 2^48 or whatever, so that you can't get an exact frequency match to any number that isn't a power of two.

I'd be willing to bet that most DDS chips are FPGAs or CPUs where you
can do whatever you like.

Well i suppose you could look through the data sheets of a few dedicated
DDS ICs. Like:

<http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds/products/index.html>

<http://www.intersil.com/en/products/timing-and-digital/dsp/dsp-synthesizers/ISL5314.html#00.html>

It seems that Analog Devices pretty much owns the market, but seems to
have about 50 or so base models. Found some Intersil as well.

Of course there is Wikipedia but they miss a lot or even get some stuff
wrong. It points to a good tutorial though:

<http://www.ieee.li/pdf/essay/dds.pdf>

?-)

 

[rickman]

On 9/16/2014 8:52 PM, josephkk wrote:

On Tue, 16 Sep 2014 15:25:36 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/15/2014 7:03 PM, Bill Sloman wrote:
On Tuesday, 16 September 2014 00:26:02 UTC+10, Piotr Wyderski wrote:
Gerhard Hoffmann wrote:

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

IMHO you don't need to implement the entire counter in BCD.
All you need is a binary counter + a simple compare/reset
circuit to reset the counter after 10e6 steps. The representation
should have no influence on the operating principle. Am I wrong?

I don't think so. I think the point that was being made was that most DDS chips have a fixed binary modulus or 2^32 or 2^48 or whatever, so that you can't get an exact frequency match to any number that isn't a power of two.

I'd be willing to bet that most DDS chips are FPGAs or CPUs where you
can do whatever you like.

Well i suppose you could look through the data sheets of a few dedicated
DDS ICs. Like:

http://www.analog.com/en/rfif-components/direct-digital-synthesis-dds/products/index.html

http://www.intersil.com/en/products/timing-and-digital/dsp/dsp-synthesizers/ISL5314.html#00.html

It seems that Analog Devices pretty much owns the market, but seems to
have about 50 or so base models. Found some Intersil as well.

Of course there is Wikipedia but they miss a lot or even get some stuff
wrong. It points to a good tutorial though:

http://www.ieee.li/pdf/essay/dds.pdf

You seem to be missing my point. I am saying that many DDS circuits are
NOT dedicated chips. They are easily built in FPGAs and are even
implemented in software using CPU chips. Dedicated DDS chips likely
have a small share of the total DDS designs.

I did look at the IEEE link and noticed the paper talks about
"truncated" phase accumulator outputs. It made me remember that the
last DDS design I did was for a 24 bit ADC/DAC and my look up table
capacity was quite limited. I implemented table folding and performed
linear interpolation to squeeze as much as I could from my resources.

I'm remembering more of the details now. I didn't want to use a binary
accumulator because it would not give me exact rates for the CODEC
sample rates in use (multiples of 8 kHz). So the upper N bits were
binary but the lower bits had a factor of 3 and maybe some 5s. The
binary section had 2 bits to implement the table folding and the rest
were used in the table lookup. Some of the lower bits were used for
interpolation. The end result was rather better than I first had feared.

--

Rick

 

[rickman]

On 9/16/2014 6:45 PM, Phil Hobbs wrote:

Honestly, Rick, is chewing on people's ankles like this the most
interesting thing you can find to do?

So why are you chewing on the ankles of the ankle biter?

--

Rick

 

[rickman]

On 9/16/2014 7:01 PM, Maynard A. Philbrook Jr. wrote:

In article <lva7n7$in1$2@dont-email.me>, gnuarm@gmail.com says...

On 9/16/2014 4:45 PM, rickman wrote:
On 9/16/2014 4:52 AM, Jan Panteltje wrote:
On a sunny day (Tue, 16 Sep 2014 00:39:45 +0200) it happened Gerhard
Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote in
c7p85hF8ojU1@mid.individual.net>:


On 9/15/2014 2:40 PM, Jan Panteltje wrote:

I think this is nice:
http://www.arrl.org/files/file/Technology/ard/rohde94.pdf
I always use JFET oscillators.

I almost never do. Bipolars are much more predictable.

That is is true,
but even then I found these JFET oscilators are very stable and noise
free.
You can use those in parallel too:
http://panteltje.com/pub/lighting_a_LED_with_a_candle_IMG_3604.GIF
Not exactly a 'low noise' application,
but for sure a 'low voltage application'.

http://panteltje.com/pub/lighting_a_LED_with_a_candle_setup_IMG_3607.GIF

I'm afraid I can't read your schematic. How are the FETs connected to
the transformer? It looks like all the gates, all the drains and the
two coils of the transformer are all shorted together.

Opps, make that all the gates and all the sources...

And what's the problem with that?

The gates and sources shorted together? I'm not familiar with the
common gate-source amplifier configuration. I thought I was just not
reading the schematic correctly. I think this makes the device into a
resistor, no? I could see a negative resistance oscillating maybe. I
just have never seen this before.

--

Rick

 

[ChesterW]

On 9/16/14, 2:39 PM, Gerhard Hoffmann wrote:

Am 16.09.2014 um 17:27 schrieb John Larkin:

This is cool:

https://dl.dropboxusercontent.com/u/53724080/Software/PhaseNoise.exe

It was done by one of the s.e.d. guys some time ago; Jeroen? It lets
you convert a phase noise curve to RMS jitter.


Rene Tschaggelar from Switzerland.
http://www.ibrtses.com/products/PhaseNoise102.exe

Looks like his website is slowly decomposing.
But I have no right to complain.

Gerhard

That's neat. Thanks.
<salute Büro>

ChesterW

 

[Jan Panteltje]

On a sunny day (Tue, 16 Sep 2014 08:27:45 -0700) it happened John Larkin
<jlarkin@highlandtechnology.com> wrote in
<g4lg1atur5r445ea12d3odk2hiu0ac52un@4ax.com>:

This is cool:

https://dl.dropboxusercontent.com/u/53724080/Software/PhaseNoise.exe

It was done by one of the s.e.d. guys some time ago; Jeroen? It lets
you convert a phase noise curve to RMS jitter.

John, I cannot find the original posting of you (yesterday?) with the laser building setup,
but I will try to give my (probably wrong) opinion on that setup here anyway.
You can verbatim giveittothem as far as I am concerned.

My simple "understanding"
1) they want to fire some lasers at a time where the _optical_ pulses reach the target at the same time.
maybe they try fusion that way or whatever.

Here it goes:
Top down does not work (but you already know that, but do they?).

This is how *I* would go about it.

2) there is no such thing as 'absolute time', so fuck any difference between absolute time (GPS wise) and when they reach fusion,
lets say the press will forgive them to be a second or two late.

So, as you want to control room temperature the best place for a thermostat is in the room,
IN THE SAME WAY
assuming they have some smaller guide (alignment whatever) lasers that can also fire on a pulse,
put optical detectors as close to the target as possible, one looking at each laser.
Repeatedly trigger one 'guide' laser from wherever (moon if must be), and then use a feedback signal (DC control voltage)
to align the other optical pulses so they co-incide as good as possible (femto, atta, you name it), and then
when this phase lock in the guide lasers is accurate enough, fire the big ones.
That is all.

It does not create so many jobs for industries (like yours), but might make it easier to get the pulses at the same time.
no jippyyes (GPS ), no pee-pee-esses, no problems.

OK, the reason Von Braun reached the moon and managed to get people back is that he was interested in the result,
not so much in the job creation aspect (of creating a monster project).

And I do not even know if all that laser shooting will ever lead to sustainable fusion.

PS I came up with this in bed last night before falling asleep.
Amazing ain't it!

 

[Jan Panteltje]

On a sunny day (Tue, 16 Sep 2014 16:45:59 -0400) it happened rickman
<gnuarm@gmail.com> wrote in <lva7in$in1$1@dont-email.me>:


>I'm afraid

So what

 

[Jan Panteltje]

On a sunny day (Tue, 16 Sep 2014 16:48:23 -0400) it happened rickman
<gnuarm@gmail.com> wrote in <lva7n7$in1$2@dont-email.me>:

On 9/16/2014 4:45 PM, rickman wrote:
On 9/16/2014 4:52 AM, Jan Panteltje wrote:
On a sunny day (Tue, 16 Sep 2014 00:39:45 +0200) it happened Gerhard
Hoffmann
ghf@hoffmann-hochfrequenz.de> wrote in
c7p85hF8ojU1@mid.individual.net>:


On 9/15/2014 2:40 PM, Jan Panteltje wrote:

I think this is nice:
http://www.arrl.org/files/file/Technology/ard/rohde94.pdf
I always use JFET oscillators.

I almost never do. Bipolars are much more predictable.

That is is true,
but even then I found these JFET oscilators are very stable and noise
free.
You can use those in parallel too:
http://panteltje.com/pub/lighting_a_LED_with_a_candle_IMG_3604.GIF
Not exactly a 'low noise' application,
but for sure a 'low voltage application'.

http://panteltje.com/pub/lighting_a_LED_with_a_candle_setup_IMG_3607.GIF

I'm afraid I can't read your schematic. How are the FETs connected to
the transformer? It looks like all the gates, all the drains and the
two coils of the transformer are all shorted together.

Opps, make that all the gates and all the sources...

I have repeatedly wondered iy you are still in highschool or kindergarten?

 

[rickman]

On 9/17/2014 3:13 AM, Jan Panteltje wrote:

On a sunny day (Tue, 16 Sep 2014 16:45:59 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lva7in$in1$1@dont-email.me>:


I'm afraid

So what

What the heck is wrong with *you*? I ask you to explain a hand drawn
schematic that I can't understand and you get weird. jeeze

I was hoping to understand what you had done.

--

Rick

 

[Jan Panteltje]

On a sunny day (Tue, 16 Sep 2014 18:25:52 +0100) it happened "Kevin Aylward"
<ExtractkevinRemove@kevinaylward.co.uk> wrote in
<Q_2dnSi3QYMC74XJnZ2dnUVZ8lKdnZ2d@bt.com>:

So, for example, a 10MHz xtal VCO fed into tanks to multiple up, looks like
a N*F VCO. This combined HF VCO could be locked in a PLL with your incoming
10MHz, for example.

I would guess that your incoming 10 MHz has a low frequency (< 1Hz) phase
noise way below that which a standard xtal oscillator has. Otherwise, I
still wont understand why 10 mili Hz noise bothers you. Noise ramps up at
30db/dec typically below 100Hz.

Well, yes, multiplying will also multiply any deviation in frequency of course.

I can say this about LC based UHF VCOs:
I use for example the Firenza vco190-1572t.pdf at 1.5 GHz (GPS frequency):

Frequency Range - 1540 1572 1605 MHz X
Tuning Voltage:
1540 MHz 1 1.4 Vdc X
1605 MHz 3.6 3.9 Vdc X
Tuning Sensitivity - 29 34 39 MHz/V X
Output Power - -3 0 3 dBm X
Output Phase Noise:
10 kHz -106 -100 dBc/Hz <--------------------
100 kHz -128 -122 dBc/Hz X <--------------------
Power Supply - 4.9 5 5.1 Volts
Supply Current - 23 30 mA X
Harmonic Suppression:
2nd Harmonic -15 -12 dBc X
3rd Harmonic -20 -12 dBc X
Spurious (Non-Harmonic) - -100 dBc
Frequency Pushing - 4.9-5.1 V 0.2 1 MHz p-p
Frequency Pulling - 12 dB RL 0.2 1 MHz p-p
Tuning Port Capacitance - 100 pF
Output Impedance - 50

Those are 12 $ or so on ebay.
Picture here
http://panteltje.com/panteltje/raspberry_pi_dvb-s_transmitter/raspberry_pi_datv_transmitter_test_setup_IMG_3937.JPG

It is the golden postage stamp size square on the right with the ground wire on it.
After additional filtering of the supply the contsellation (free running!) looks like this:
http://panteltje.com/panteltje/raspberry_pi_dvb-s_transmitter/

So, I have not done the math to find pico seconds, but it is good enough for digital TV.
How much is 2 degrees of 1.5 GHz?
(1 / 1,500,000,000) * (2 / 360) = 3.7037e-12
mm
Free running that is.
After mixing with data carrier, transmission path, so its better.
It should be, else you lose the constellation.
Imagine with a 256 dots constellation, DVB-T, DVB-S is simple.

Well, its working, what do you say:
http://panteltje.com/panteltje/raspberry_pi_dvb-s_transmitter/
Yes Rick, you cannot read the circuit diagram, I know
But you have picjures, enjoy!

QUIZ:
How many SMDs are on this board.

 

[Jan Panteltje]

On a sunny day (Wed, 17 Sep 2014 03:19:11 -0400) it happened rickman
<gnuarm@gmail.com> wrote in <lvbclv$8dj$2@dont-email.me>:

On 9/17/2014 3:13 AM, Jan Panteltje wrote:
On a sunny day (Tue, 16 Sep 2014 16:45:59 -0400) it happened rickman
gnuarm@gmail.com> wrote in <lva7in$in1$1@dont-email.me>:


I'm afraid

So what

What the heck is wrong with *you*? I ask you to explain a hand drawn
schematic that I can't understand and you get weird. jeeze

I was hoping to understand what you had done.

Did you not see the words "in parallel" ?
John is right, you really need to pick up some hobby.