PLL tricks

[Phil Hobbs]

On 09/15/2014 01:30 PM, Kevin Aylward wrote:

"Phil Hobbs" wrote in message news:54160BAF.3090808@electrooptical.net...

On 9/14/2014 2:02 PM, Kevin Aylward wrote:
"Gerhard Hoffmann" wrote in message
news:c7l84fFsqprU1@mid.individual.net...

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

PLL are useful when you want programmability in frequency and no
inductors,
but 80 year old LC tank technology blows PLL away in terms of noise
performance. For example, meeting -150 dBc (30fs jitter) flat band
phase
noise at 2.5GHz is, essentially, not achievable with PLL techniques,
not
that I am giving anything away on one of my current projects...

http://cds.linear.com/docs/en/datasheet/6948f.pdf

shows only -100dBc/Hz on its performance curves.

???
on page 8 I see the 3 and 4 GHz units break the -150 dBc/Hz
at 10 MHz offset, still linearly sinking towards the flat
noise floor.

Ah... I should add... flat band noise with a multiplication of times 9
Multiplying up has an inherent theoretical noise increase of 20.log(mult
ratio), so a times 9 is going to increase the basic oscillator phase
noise by around 20dB, irrespective of any added noise of the processing.

But not the jitter. The reason the phase noise goes up is that the
jitter stays more or less the same, but the period goes down by a
factor N, so the phase fluctuations increase by N times.

Sure.

Going back to "Ultra low noise claim of the 6948f" data sheet above, I
now see that at ~2.5Ghz it is -100dBc at 100k offset, and -130dBc at
1MHz. A decent x9 (277Mhz->2.5Ghz) LC tank design should come it at
around -145 dBc at those frequency offsets. So ultra low noise appears
to be relative to the claimer

Inevitably. The marketing department again. Of course a nice YIG-tuned
oscillator like the ones in the HP8568 can be >100 dB down at 100 Hz.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[John Larkin]

On Mon, 15 Sep 2014 13:52:27 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/15/2014 01:30 PM, Kevin Aylward wrote:
"Phil Hobbs" wrote in message news:54160BAF.3090808@electrooptical.net...

On 9/14/2014 2:02 PM, Kevin Aylward wrote:
"Gerhard Hoffmann" wrote in message
news:c7l84fFsqprU1@mid.individual.net...

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

PLL are useful when you want programmability in frequency and no
inductors,
but 80 year old LC tank technology blows PLL away in terms of noise
performance. For example, meeting -150 dBc (30fs jitter) flat band
phase
noise at 2.5GHz is, essentially, not achievable with PLL techniques,
not
that I am giving anything away on one of my current projects...

http://cds.linear.com/docs/en/datasheet/6948f.pdf

shows only -100dBc/Hz on its performance curves.

???
on page 8 I see the 3 and 4 GHz units break the -150 dBc/Hz
at 10 MHz offset, still linearly sinking towards the flat
noise floor.

Ah... I should add... flat band noise with a multiplication of times 9
Multiplying up has an inherent theoretical noise increase of 20.log(mult
ratio), so a times 9 is going to increase the basic oscillator phase
noise by around 20dB, irrespective of any added noise of the processing.

But not the jitter. The reason the phase noise goes up is that the
jitter stays more or less the same, but the period goes down by a
factor N, so the phase fluctuations increase by N times.

Sure.

Going back to "Ultra low noise claim of the 6948f" data sheet above, I
now see that at ~2.5Ghz it is -100dBc at 100k offset, and -130dBc at
1MHz. A decent x9 (277Mhz->2.5Ghz) LC tank design should come it at
around -145 dBc at those frequency offsets. So ultra low noise appears
to be relative to the claimer

Inevitably. The marketing department again. Of course a nice YIG-tuned
oscillator like the ones in the HP8568 can be >100 dB down at 100 Hz.

Cheers

Phil Hobbs

I never really understood yigs. How do you control the magnetic field
to super-precise levels?


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Phil Hobbs]

On 09/15/2014 02:18 PM, John Larkin wrote:

On Mon, 15 Sep 2014 13:52:27 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/15/2014 01:30 PM, Kevin Aylward wrote:
"Phil Hobbs" wrote in message news:54160BAF.3090808@electrooptical.net...

On 9/14/2014 2:02 PM, Kevin Aylward wrote:
"Gerhard Hoffmann" wrote in message
news:c7l84fFsqprU1@mid.individual.net...

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

PLL are useful when you want programmability in frequency and no
inductors,
but 80 year old LC tank technology blows PLL away in terms of noise
performance. For example, meeting -150 dBc (30fs jitter) flat band
phase
noise at 2.5GHz is, essentially, not achievable with PLL techniques,
not
that I am giving anything away on one of my current projects...

http://cds.linear.com/docs/en/datasheet/6948f.pdf

shows only -100dBc/Hz on its performance curves.

???
on page 8 I see the 3 and 4 GHz units break the -150 dBc/Hz
at 10 MHz offset, still linearly sinking towards the flat
noise floor.

Ah... I should add... flat band noise with a multiplication of times 9
Multiplying up has an inherent theoretical noise increase of 20.log(mult
ratio), so a times 9 is going to increase the basic oscillator phase
noise by around 20dB, irrespective of any added noise of the processing.

But not the jitter. The reason the phase noise goes up is that the
jitter stays more or less the same, but the period goes down by a
factor N, so the phase fluctuations increase by N times.

Sure.

Going back to "Ultra low noise claim of the 6948f" data sheet above, I
now see that at ~2.5Ghz it is -100dBc at 100k offset, and -130dBc at
1MHz. A decent x9 (277Mhz->2.5Ghz) LC tank design should come it at
around -145 dBc at those frequency offsets. So ultra low noise appears
to be relative to the claimer

Inevitably. The marketing department again. Of course a nice YIG-tuned
oscillator like the ones in the HP8568 can be >100 dB down at 100 Hz.

Cheers

Phil Hobbs

I never really understood yigs. How do you control the magnetic field
to super-precise levels?

I've never designed one myself. Usually there are two coils, one coarse
and slow, the other fine and fast. It's easy to make something quiet if
you can make it very slow in the process.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[John Larkin]

On Mon, 15 Sep 2014 13:47:32 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/15/2014 01:31 PM, Kevin Aylward wrote:
"Phil Hobbs" wrote in message news:54160E66.80808@electrooptical.net...

On 9/14/2014 8:43 AM, upsidedown@downunder.com wrote:
On Sun, 14 Sep 2014 13:22:23 +0100, Mike Perkins <spam@spam.com
wrote:

Frequency locking isn't difficult. Time locking to picoseconds is.
http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf

What I will say though, is multiplying up by harmonic selection
from LC
tanks gives orders of lower phase noise/jitter than a PLL.

Won't LC tanks have horrendous temperature coefficients?

Not that bad after all. Assuming a LC Q-factor of 100, you will have a
1 % -3 dB bandwidth. That would allow a 10000 ppm drift across the
temperature range (100 ppm/C across 100 C). After all, you are
interested in the harmonics of the crystal oscillator, not the filter
performance.

In the words of Rudyard Kipling, "Not so, but far otherwise." For a
single section the phase shift across the width of the resonance is on
the order of 1 radian, so in terms of phase, a filter with a Q of 100
magnifies the component tempcos by roughly 100 times. A time shift of
1 ps is about a milliradian at 155 MHz. Typical inductor tempcos of
+100 ppm/C will give you a phase shift of something like

dPhi/dT ~ Q * dL/dT
or 0.01 radian/K, i.e. 10 ps/K.

You will need to give me a heads up on what applications this delay
change will matter. Temperature changes are typically sub Hz. Once
equipment warms up, it could be minutes for a one degree change in
temperature. The steady state frequency won't change, its n x input f.
Considering that say, a 10MHz oscillator might hit -100 dBc at 10 Hz
offset compared to its wonderful -160dBc flatband (100kHz +) , systems,
in general have to be a lot more tolerant of close in phase noise.

Its a fact that many main stream high performance xtal oscillator
vendors use LC tanks to up-convert the xtal frequency to achieve lower
noise than is available from a PLL. You seem to be implying that there
is some flaw with this approach for some applications. I would be
interested to know the details.

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

In John's application, it will make the 10 MHz BPF the dominant source
of drift in the whole board, because it's outside the loop.

Cheers

Phil Hobbs

Right. I need a 10 MHz bandpass filter with really small delay vs
temperature behavior. Another annoyance, designing a filter and
analyzing its sensitivities and compensating inductors with NTC caps,
or something. Probably I'll measure ambient temp and let the uP tweak
overall delay to nominally zero. That sort of thing will typically
result in a 5:1, maybe even 10:1, TC reduction. I don't want to
temperature cycle units in production, so the slope compensation would
be determined on the first unit and applied to all the rest, if
possible.

Inductors of the type we'd use here seem to have TCs in the (roughly)
+120 PPM/K sort of range.




--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Jan Panteltje]

On a sunny day (Mon, 15 Sep 2014 13:22:06 -0400) it happened Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote in
<f18e1ati81bdgbag3ors01c1m2j6fd5s1m@4ax.com>:

On 15 Sep 2014 10:08:14 GMT, Jasen Betts <jasen@xnet.co.nz> wrote:

On 2014-09-14, John Larkin <jlarkin@highlandtechnology.com> wrote:
On Sun, 14 Sep 2014 20:06:44 GMT, Jan Panteltje <panteltje@yahoo.com
wrote:


How come the Enterprise, no matter how badly it was shot up, never
lost pressurization and never lost its artificial gravity generator?

And why did they always beam into derelict spaceships and alien
planets that had breathable atmospheres and Earth-level gravity?

Why were no babies ever born on the Enterprise? Why did nobody ever
bleed or vomit? Did they have unisex rest rooms? Did they have
bathtubs? Where were the trash cans? Were snacks not allowed on the
bridge?

The producer didn't have the special-effects budget.

Apparently some snacks were allowed:

https://www.youtube.com/watch?v=Z1EZK0CKtK4

Nice, watched all 4 episodes.

 

[Lasse Langwadt Christense]

Den tirsdag den 16. september 2014 00.26.41 UTC+2 skrev John Larkin:

On Mon, 15 Sep 2014 02:03:12 +0200, Dimitrij Klingbeil

nospam@no-address.com> wrote:



On 15.09.2014 01:02, rickman wrote:

On 9/14/2014 3:49 PM, John Larkin wrote:

On Sun, 14 Sep 2014 15:22:10 -0400, rickman <gnuarm@gmail.com

wrote:



To fire things on time. My PLL can clean up jitter on the 10 MHz

reference.



A very vague explanation. You are using a 1 ps accurate rifle to

hit a target that is moving around by 10's of ps. Then you want to

determine where the target is by watching the rifle.



I think you can have a rifle that is not so good as 1 ps and still

get the same result. It all runs through the same filter.



Well, John did not say what exactly he's trying to fire, but it looks

like he means the "rifle" with the 500 TW. That's a highly distributed

"rifle" with 192 "chambers" being fired synchronously. John's probably

building the "mechanism" responsible for the action of each "pin".



(John, correct me if I'm wrong ...)





Yes, this is for NIF. Some years back, we designed the VME modules

that receive the OC3 fiberoptic master timing signals and fire devices

all over the facility. We phase-lock a 155.52 MHz XO to the data

stream, and decode timing packets.



Now I'm looking into building the other end, the data generator.



http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf





The one thing that strikes me as really odd, is that they want the thing

to be synchronized to a 10MHz signal over coax lines. The use of a

higher frequency and fiber optics would likely provide a much better

distribution of the timing signal.



Maybe John should consider running his own ovenized "master oscillator"

at a suitable (higher) frequency and PLLing it to the incoming 10 MHz

with a very long time constant (some people on the well-known Time Nuts

mailing list temperature-stabilize the ovens of their own GPSDOs to

millikelvins and then run the PLLs with filter time constants on the

order of hours or even days in order to keep ADEV as low as they can,

but then they only have a PPS signal to start from). Having 10 MHz to

start from is obviously much better than 1 PPS, so there's no need for

hours or days of PLL stabilization time, but still, using a more short

term stable (translate: less jittery) internal reference is probably

something to consider, before starting to synthesize the 155 MHz.



I'd love to buy a 155.52 MHz VCXO that has really low jitter. I have a

10 MHz SRS OCXO (replacement for an old HP can) that has a couple ps

RMS jitter a full second out. I could discipline that at a very low

loop bandwidth, so an 80 KHz phase detector would be no problem. But

the really good SC-cut crystals run in the low MHz range.

first hit on google, http://www.accusilicon.com/155.52MHz.htm

-Lasse

 

[Jan Panteltje]

On a sunny day (Mon, 15 Sep 2014 13:52:27 -0400) it happened Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote in
<5417275B.3010101@electrooptical.net>:

Going back to "Ultra low noise claim of the 6948f" data sheet above, I
now see that at ~2.5Ghz it is -100dBc at 100k offset, and -130dBc at
1MHz. A decent x9 (277Mhz->2.5Ghz) LC tank design should come it at
around -145 dBc at those frequency offsets. So ultra low noise appears
to be relative to the claimer

Inevitably. The marketing department again. Of course a nice YIG-tuned
oscillator like the ones in the HP8568 can be >100 dB down at 100 Hz.

I think this is nice:
http://www.arrl.org/files/file/Technology/ard/rohde94.pdf
I always use JFET oscillators.

And as to cables adding phase noise due to vibration or even gravity:
http://www.ieee-uffc.org/frequency-control/learning/Tutorial_Rev_Q.PDF

 

[rickman]

On 9/15/2014 9:23 AM, Phil Hobbs wrote:

On 9/15/2014 12:24 AM, rickman wrote:
On 9/14/2014 11:58 PM, John Larkin wrote:
On Sun, 14 Sep 2014 23:29:59 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 9:30 PM, John Larkin wrote:
On Sun, 14 Sep 2014 20:56:34 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways.
First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the
divided
clock
is not an issue? It is not being used to clock anything. It
is only
being used to isolate the actual clock edges by enabling the
FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my
universe. John
specifically said that you needed to drive the DFF
differentially to get
the good jitter numbers, so despite having CLK and /CLK pins,
there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider
output into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being
divided
down. Otherwise you get 1 full clock cycle of jitter in the
enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything
so idiotic.

How would that break the PLL? The reference clock is sampled by
the D
input clocked by the VCXO clock. The divided signal has to be an
enable
on the FF or it won't work because of the inherent delays in
generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in
even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I
think we
are not talking about the same circuits.

About like this:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/BangBang_PLL.JPG



So where is the output?

Wherever I need it to be. What a PITA you are.

By using the divided clock to clock the reference you have added an
unspecified delay which will vary with time, temperature, process and
voltage. Is all this going to give you the 1 ps spec you need? Is
there really no part available with an enable? That gets around the
problem totally.

The problem is imaginary. Reclocking the divider output from the VCXO
gets rid of all the divider junk, and the resynchronized output has the
same jitter as the VCXO, plus whatever very small contribution comes
from the D-flop. If it existed, a DFF with a clock enable would
function in much the same way. What difference do you see between the
two cases? The DFF output is synchronous with the VCXO either way.

The difference is that the output of the PD can have jitter and it has
very little effect on the result. I don't know how much jitter and
delay will be introduced by the reclocking FF, but it directly impacts
the sampling by the PD which is what John seems to want to minimize.

John acknowledges that the reference will have jitter and arbitrary
delay. So I suppose none of this matters much.

--

Rick

 

[rickman]

On 9/15/2014 9:24 AM, Phil Hobbs wrote:

On 9/14/2014 11:31 PM, rickman wrote:
On 9/14/2014 9:41 PM, Phil Hobbs wrote:
On 9/14/2014 8:56 PM, rickman wrote:
On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First,
the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is
only
being used to isolate the actual clock edges by enabling the
FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John
specifically said that you needed to drive the DFF differentially to
get
the good jitter numbers, so despite having CLK and /CLK pins,
there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output
into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being
divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything
so idiotic.

How would that break the PLL? The reference clock is sampled by
the D
input clocked by the VCXO clock. The divided signal has to be an
enable
on the FF or it won't work because of the inherent delays in
generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in
even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.



*----------------<----------------------------------------*
| |
VCXO *-----* *-----* *-------* |
155.52 MHz ->-- /1944 ->-|D Q|------|D Q|---| LOOP |----*
| | | | | |FILTER |
V *--^--* *--^--* *-------*
| | |
*------->-------* *---<----10MHz REF
Resynch B-B phase det

With maybe a second DFF stage between the phase detector and the loop
filter, to get rid of any noise caused by metastability.

Where is the output?

From the VCXO.

Ok, so how much does the resync FF add to the jitter? It seems there is
no concern with the actual delay, just the jitter.

--

Rick

 

[Bill Sloman]

On Tuesday, 16 September 2014 00:26:02 UTC+10, Piotr Wyderski wrote:

Gerhard Hoffmann wrote:

With a BCD DDS your step size can be f_clock / 10e6 and that
that is an advantage if you need a frequency that can be
exactly written in a few decimal digits.

IMHO you don't need to implement the entire counter in BCD.
All you need is a binary counter + a simple compare/reset
circuit to reset the counter after 10e6 steps. The representation
should have no influence on the operating principle. Am I wrong?

I don't think so. I think the point that was being made was that most DDS chips have a fixed binary modulus or 2^32 or 2^48 or whatever, so that you can't get an exact frequency match to any number that isn't a power of two.

In general the modulus doesn't have to be fixed, let alone a power of two, and - for example - the AD9915 has an arrangement that lets you set up pretty much any modulus you want. If you are rolling your own DDS you do have the same freedom.

--
Bill Sloman, Sydney

 

[John Larkin]

On Mon, 15 Sep 2014 14:46:27 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/15/2014 9:24 AM, Phil Hobbs wrote:
On 9/14/2014 11:31 PM, rickman wrote:
On 9/14/2014 9:41 PM, Phil Hobbs wrote:
On 9/14/2014 8:56 PM, rickman wrote:
On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First,
the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is
only
being used to isolate the actual clock edges by enabling the
FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John
specifically said that you needed to drive the DFF differentially to
get
the good jitter numbers, so despite having CLK and /CLK pins,
there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output
into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being
divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything
so idiotic.

How would that break the PLL? The reference clock is sampled by
the D
input clocked by the VCXO clock. The divided signal has to be an
enable
on the FF or it won't work because of the inherent delays in
generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in
even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.



*----------------<----------------------------------------*
| |
VCXO *-----* *-----* *-------* |
155.52 MHz ->-- /1944 ->-|D Q|------|D Q|---| LOOP |----*
| | | | | |FILTER |
V *--^--* *--^--* *-------*
| | |
*------->-------* *---<----10MHz REF
Resynch B-B phase det

With maybe a second DFF stage between the phase detector and the loop
filter, to get rid of any noise caused by metastability.

Where is the output?

From the VCXO.

Ok, so how much does the resync FF add to the jitter? It seems there is
no concern with the actual delay, just the jitter.

I'd guess that the FPGA divide-by-1944 might have 5 or 10 ps RMS
jitter, and will have a ghastly TC, 10s of ps per degree C. The ECL
resync flop cleans all that up.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[rickman]

On 9/15/2014 3:08 PM, John Larkin wrote:

On Mon, 15 Sep 2014 14:46:27 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/15/2014 9:24 AM, Phil Hobbs wrote:
On 9/14/2014 11:31 PM, rickman wrote:
On 9/14/2014 9:41 PM, Phil Hobbs wrote:
On 9/14/2014 8:56 PM, rickman wrote:
On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First,
the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is
only
being used to isolate the actual clock edges by enabling the
FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John
specifically said that you needed to drive the DFF differentially to
get
the good jitter numbers, so despite having CLK and /CLK pins,
there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output
into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being
divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything
so idiotic.

How would that break the PLL? The reference clock is sampled by
the D
input clocked by the VCXO clock. The divided signal has to be an
enable
on the FF or it won't work because of the inherent delays in
generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in
even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.



*----------------<----------------------------------------*
| |
VCXO *-----* *-----* *-------* |
155.52 MHz ->-- /1944 ->-|D Q|------|D Q|---| LOOP |----*
| | | | | |FILTER |
V *--^--* *--^--* *-------*
| | |
*------->-------* *---<----10MHz REF
Resynch B-B phase det

With maybe a second DFF stage between the phase detector and the loop
filter, to get rid of any noise caused by metastability.

Where is the output?

From the VCXO.

Ok, so how much does the resync FF add to the jitter? It seems there is
no concern with the actual delay, just the jitter.

I'd guess that the FPGA divide-by-1944 might have 5 or 10 ps RMS
jitter, and will have a ghastly TC, 10s of ps per degree C. The ECL
resync flop cleans all that up.

That doesn't answer the question. How much jitter does the resynch FF
add to the VCXO clock jitter? Do you have a number or at least an order
of magnitude?

--

Rick

 

On Mon, 15 Sep 2014 13:22:06 -0400, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

On 15 Sep 2014 10:08:14 GMT, Jasen Betts <jasen@xnet.co.nz> wrote:

On 2014-09-14, John Larkin <jlarkin@highlandtechnology.com> wrote:
On Sun, 14 Sep 2014 20:06:44 GMT, Jan Panteltje <panteltje@yahoo.com
wrote:


How come the Enterprise, no matter how badly it was shot up, never
lost pressurization and never lost its artificial gravity generator?

And why did they always beam into derelict spaceships and alien
planets that had breathable atmospheres and Earth-level gravity?

Why were no babies ever born on the Enterprise? Why did nobody ever
bleed or vomit? Did they have unisex rest rooms? Did they have
bathtubs? Where were the trash cans? Were snacks not allowed on the
bridge?

The producer didn't have the special-effects budget.

Apparently some snacks were allowed:

https://www.youtube.com/watch?v=Z1EZK0CKtK4

I don't think so. I think by that time they'd learned their lesson:

http://snltranscripts.jt.org/78/78ppepsi.phtml

(sorry, couldn't find a free video)

 

On Mon, 15 Sep 2014 07:32:39 -0700, John Larkin
<jlarkin@highlandtechnology.com> wrote:

On Mon, 15 Sep 2014 01:45:05 -0400, "Tom Miller"
tmiller11147@verizon.net> wrote:


"John Larkin" <jlarkin@highlandtechnology.com> wrote in message
news:j8gc1a9n6pq14t5jr17lbmlp38jma1n3ri@4ax.com...
On Sun, 14 Sep 2014 20:56:34 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John
specifically said that you needed to drive the DFF differentially to
get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output into
D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an
enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in even
an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.

About like this:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/BangBang_PLL.JPG



--

What is the 1 PPS for? I must have missed that message.



I did mention that somewhere. Ultimately I have to send out fiberoptic
data frames that include time-of-day fields. The GPS box gives me 10
MHz and 1 PPS references, and an occasional Ethernet message will give
me time to within 1 second. The FPGA contains the counters and logic
and stuff, and a uP manages things at the millisecond level. The whold
project is pretty straightforward except for the PLL.

The trick is to make everything stable to picoseconds. The entire
system error budget is 100 ps, of which I can claim a small share.

Have you considered Ethernet/AVB or perhaps the 802.1AS subset?

 

[Phil Hobbs]

On 9/15/2014 2:44 PM, rickman wrote:

On 9/15/2014 9:23 AM, Phil Hobbs wrote:
On 9/15/2014 12:24 AM, rickman wrote:
On 9/14/2014 11:58 PM, John Larkin wrote:
On Sun, 14 Sep 2014 23:29:59 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 9:30 PM, John Larkin wrote:
On Sun, 14 Sep 2014 20:56:34 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways.
First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the
divided
clock
is not an issue? It is not being used to clock anything. It
is only
being used to isolate the actual clock edges by enabling the
FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my
universe. John
specifically said that you needed to drive the DFF
differentially to get
the good jitter numbers, so despite having CLK and /CLK pins,
there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider
output into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being
divided
down. Otherwise you get 1 full clock cycle of jitter in the
enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything
so idiotic.

How would that break the PLL? The reference clock is sampled by
the D
input clocked by the VCXO clock. The divided signal has to be an
enable
on the FF or it won't work because of the inherent delays in
generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in
even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I
think we
are not talking about the same circuits.

About like this:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/BangBang_PLL.JPG




So where is the output?

Wherever I need it to be. What a PITA you are.

By using the divided clock to clock the reference you have added an
unspecified delay which will vary with time, temperature, process and
voltage. Is all this going to give you the 1 ps spec you need? Is
there really no part available with an enable? That gets around the
problem totally.

The problem is imaginary. Reclocking the divider output from the VCXO
gets rid of all the divider junk, and the resynchronized output has the
same jitter as the VCXO, plus whatever very small contribution comes
from the D-flop. If it existed, a DFF with a clock enable would
function in much the same way. What difference do you see between the
two cases? The DFF output is synchronous with the VCXO either way.

The difference is that the output of the PD can have jitter and it has
very little effect on the result. I don't know how much jitter and
delay will be introduced by the reclocking FF, but it directly impacts
the sampling by the PD which is what John seems to want to minimize.

You have to divide with _something_, and it would be hard for a part
with a 300 ps propagation delay and subpicosecond decision time to
introduce much.

John acknowledges that the reference will have jitter and arbitrary
delay. So I suppose none of this matters much.

Cheers

Phil Hobbs


--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[ChesterW]

On 9/14/14, 8:41 PM, Phil Hobbs wrote:

On 9/14/2014 8:56 PM, rickman wrote:
On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John
specifically said that you needed to drive the DFF differentially to
get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output
into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an
enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in
even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.



*----------------<----------------------------------------*
| |
VCXO *-----* *-----* *-------* |
155.52 MHz ->-- /1944 ->-|D Q|------|D Q|---| LOOP |----*
| | | | | |FILTER |
V *--^--* *--^--* *-------*
| | |
*------->-------* *---<----10MHz REF
Resynch B-B phase det

With maybe a second DFF stage between the phase detector and the loop
filter, to get rid of any noise caused by metastability.

Cheers

Phil Hobbs

It's elegant, but it seems counter-intuitive that the rather tough specs
can be met when throwing away over 99% of the phase comparison
information (1-1/125).

ChesterW

 

[Phil Hobbs]

On 9/15/2014 2:29 PM, John Larkin wrote:

On Mon, 15 Sep 2014 13:47:32 -0400, Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote:

On 09/15/2014 01:31 PM, Kevin Aylward wrote:
"Phil Hobbs" wrote in message news:54160E66.80808@electrooptical.net...

On 9/14/2014 8:43 AM, upsidedown@downunder.com wrote:
On Sun, 14 Sep 2014 13:22:23 +0100, Mike Perkins <spam@spam.com
wrote:

Frequency locking isn't difficult. Time locking to picoseconds is.
http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf

What I will say though, is multiplying up by harmonic selection
from LC
tanks gives orders of lower phase noise/jitter than a PLL.

Won't LC tanks have horrendous temperature coefficients?

Not that bad after all. Assuming a LC Q-factor of 100, you will have a
1 % -3 dB bandwidth. That would allow a 10000 ppm drift across the
temperature range (100 ppm/C across 100 C). After all, you are
interested in the harmonics of the crystal oscillator, not the filter
performance.

In the words of Rudyard Kipling, "Not so, but far otherwise." For a
single section the phase shift across the width of the resonance is on
the order of 1 radian, so in terms of phase, a filter with a Q of 100
magnifies the component tempcos by roughly 100 times. A time shift of
1 ps is about a milliradian at 155 MHz. Typical inductor tempcos of
+100 ppm/C will give you a phase shift of something like

dPhi/dT ~ Q * dL/dT
or 0.01 radian/K, i.e. 10 ps/K.

You will need to give me a heads up on what applications this delay
change will matter. Temperature changes are typically sub Hz. Once
equipment warms up, it could be minutes for a one degree change in
temperature. The steady state frequency won't change, its n x input f.
Considering that say, a 10MHz oscillator might hit -100 dBc at 10 Hz
offset compared to its wonderful -160dBc flatband (100kHz +) , systems,
in general have to be a lot more tolerant of close in phase noise.

Its a fact that many main stream high performance xtal oscillator
vendors use LC tanks to up-convert the xtal frequency to achieve lower
noise than is available from a PLL. You seem to be implying that there
is some flaw with this approach for some applications. I would be
interested to know the details.

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

In John's application, it will make the 10 MHz BPF the dominant source
of drift in the whole board, because it's outside the loop.

Cheers

Phil Hobbs

Right. I need a 10 MHz bandpass filter with really small delay vs
temperature behavior. Another annoyance, designing a filter and
analyzing its sensitivities and compensating inductors with NTC caps,
or something. Probably I'll measure ambient temp and let the uP tweak
overall delay to nominally zero. That sort of thing will typically
result in a 5:1, maybe even 10:1, TC reduction. I don't want to
temperature cycle units in production, so the slope compensation would
be determined on the first unit and applied to all the rest, if
possible.

Inductors of the type we'd use here seem to have TCs in the (roughly)
+120 PPM/K sort of range.

If you can get by with a synchronously-tuned BPF, which you probably
can, you could run a very slow delay-locked loop comparing the 10 MHz
with itself, before and after the filter, perhaps with another ECL DFF.
Tune a varactor or two with the output of that. It'd cost $15 or so
for another DFF and a couple of comparators, but that's a lot easier
than doing it with N750s.

Since the forcing would be very slow, you could run the loop
intermittently to save jitter in the intervals you really care about.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Phil Hobbs]

On 9/15/2014 5:40 PM, ChesterW wrote:

On 9/14/14, 8:41 PM, Phil Hobbs wrote:
On 9/14/2014 8:56 PM, rickman wrote:
On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is
only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John
specifically said that you needed to drive the DFF differentially to
get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output
into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being
divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an
enable
on the FF or it won't work because of the inherent delays in
generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in
even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.



*----------------<----------------------------------------*
| |
VCXO *-----* *-----* *-------* |
155.52 MHz ->-- /1944 ->-|D Q|------|D Q|---| LOOP |----*
| | | | | |FILTER |
V *--^--* *--^--* *-------*
| | |
*------->-------* *---<----10MHz REF
Resynch B-B phase det

With maybe a second DFF stage between the phase detector and the loop
filter, to get rid of any noise caused by metastability.

Cheers

Phil Hobbs

It's elegant, but it seems counter-intuitive that the rather tough specs
can be met when throwing away over 99% of the phase comparison
information (1-1/125).

ChesterW

For a constant loop bandwidth, you should get some noise averaging by
doing the phase comparison faster, I agree. However, since you have to
crank down the BW to filter out the gross amounts of ripple from a
bang-bang phase detector, I expect that it won't be that different
inside the BW.

Of course, losing all that loop bandwidth does mean that the VCXO has to
be a lot better than it would with a 10 MHz comparison frequency.

Using local feedback, i.e. a DDS-based or fractional-N loop (wide loop
BW but probably fairly horrible drift) inside an 80-kHz bang-bang loop
would relax the requirements on the VCXO proper.

This is all such fun that I may have to try building something like that.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Phil Hobbs]

On 9/15/2014 2:40 PM, Jan Panteltje wrote:

On a sunny day (Mon, 15 Sep 2014 13:52:27 -0400) it happened Phil Hobbs
pcdhSpamMeSenseless@electrooptical.net> wrote in
5417275B.3010101@electrooptical.net>:

Going back to "Ultra low noise claim of the 6948f" data sheet above, I
now see that at ~2.5Ghz it is -100dBc at 100k offset, and -130dBc at
1MHz. A decent x9 (277Mhz->2.5Ghz) LC tank design should come it at
around -145 dBc at those frequency offsets. So ultra low noise appears
to be relative to the claimer

Inevitably. The marketing department again. Of course a nice YIG-tuned
oscillator like the ones in the HP8568 can be >100 dB down at 100 Hz.

I think this is nice:
http://www.arrl.org/files/file/Technology/ard/rohde94.pdf
I always use JFET oscillators.

And as to cables adding phase noise due to vibration or even gravity:
http://www.ieee-uffc.org/frequency-control/learning/Tutorial_Rev_Q.PDF

Interesting, thanks.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[John Larkin]

On Mon, 15 Sep 2014 16:52:42 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/15/2014 3:08 PM, John Larkin wrote:
On Mon, 15 Sep 2014 14:46:27 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/15/2014 9:24 AM, Phil Hobbs wrote:
On 9/14/2014 11:31 PM, rickman wrote:
On 9/14/2014 9:41 PM, Phil Hobbs wrote:
On 9/14/2014 8:56 PM, rickman wrote:
On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First,
the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is
only
being used to isolate the actual clock edges by enabling the
FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John
specifically said that you needed to drive the DFF differentially to
get
the good jitter numbers, so despite having CLK and /CLK pins,
there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output
into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being
divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything
so idiotic.

How would that break the PLL? The reference clock is sampled by
the D
input clocked by the VCXO clock. The divided signal has to be an
enable
on the FF or it won't work because of the inherent delays in
generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in
even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.



*----------------<----------------------------------------*
| |
VCXO *-----* *-----* *-------* |
155.52 MHz ->-- /1944 ->-|D Q|------|D Q|---| LOOP |----*
| | | | | |FILTER |
V *--^--* *--^--* *-------*
| | |
*------->-------* *---<----10MHz REF
Resynch B-B phase det

With maybe a second DFF stage between the phase detector and the loop
filter, to get rid of any noise caused by metastability.

Where is the output?

From the VCXO.

Ok, so how much does the resync FF add to the jitter? It seems there is
no concern with the actual delay, just the jitter.

I'd guess that the FPGA divide-by-1944 might have 5 or 10 ps RMS
jitter, and will have a ghastly TC, 10s of ps per degree C. The ECL
resync flop cleans all that up.

That doesn't answer the question. How much jitter does the resynch FF
add to the VCXO clock jitter? Do you have a number or at least an order
of magnitude?

The MC10EP52 has a data sheet typical random jitter of 200 fs RMS, 1
ps max. I can't measure that low. Our best scope is about 1.5 ps RMS.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com