PLL tricks

[John Larkin]

On Mon, 15 Sep 2014 00:30:25 +0200, Gerhard Hoffmann
<ghf@hoffmann-hochfrequenz.de> wrote:

on the board, and of course FPGAs and such need lots of independently
regulated rails anyway. It's not especially difficult to reduce the
externally-coupled noise on a rails to well below 1 nV/sqrt(Hz),
regardless of what the input supply looks like. That's probably well
below the input-referred noise of the D-flop.

Since you are mentioning really clean supplies:
I have built a preamp to verify the noise on supplies and Vtune lines:

http://www.hoffmann-hochfrequenz.de/downloads/lono.pdf

and used it to measure the noise of batteries, simply because they are
probably the hardest test objects.


http://www.hoffmann-hochfrequenz.de/downloads/NoiseMeasurementsOnChemicalBatteries.pdf


It's not yet accesible from the rest of the website, you must know
the exact address since I'm not yet happy with the results. I see
much more 1/f noise than F.Walls from NIST, and partly 30 dB/decade.

I have used an old Avantek wideband amplifier with 57 dB gain and mixed
down the noise @100 MHz with a signal generator, ring mixer & low pass
to AF, and it was as flat as could be down to 0.1 Hz. So if it's
flat, the system shows it as flat. wierd.

regards, Gerhard

I was thinking of doing something like that with a bunch of jfets.
BF862's have about 800 pV/rthz voltage noise and very low current
noise. Less propensity to rectify RF, too.

Wish I had a use for it!


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[rickman]

On 9/14/2014 3:49 PM, John Larkin wrote:

On Sun, 14 Sep 2014 15:22:10 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 4:41 AM, Jan Panteltje wrote:
On a sunny day (Sat, 13 Sep 2014 14:28:39 -0700) it happened John Larkin
jlarkin@highlandtechnology.com> wrote in
44d91adte3vc7jipnapet6okglevfn40qm@4ax.com>:

You can't do any better than the phase comparator. So I can see why he
want's that as good as possible. But the delays introduced *after* the
phase comparator will not produce phase errors. That delay is only of
consequence to the loop stability.

Right. The dflop phase detector has such high equivalent gain that the
downstream lowpass won't add significant time error.

John, I was thinking last night about this problem,
but I quickly, for the 1 ps jitter case, got curious about your 10 MHz reference.
For sure that needs to be 'better'.
Is it a sinewave? A symmetrical square wave? Rise times?

The flip-flop phase comparators are noisy by themselves,
in precise nanosecond locking systems I have worked with, you first lock to
frequency with a simple phase comparator, and then after frequency lock
switch to a second more precise phase comparator, and sometimes even a third.
I have never done a pico second accurate lock.
Anyway after frequency lock you switch to the normal PID lock, I have used sample and hold
on a ramp for that, so you are in linear range and no 'bang bang' noise is present.
If the system is knocked out of lock, then you go back to frequency comparator etc.
For the PID case you can set gain and I and D compensation and you like.

I just read John's post where he said the reference clock will have 10's
of ps jitter or that he can add it, so what is the point of a 1 ps
accurate PD?

To fire things on time. My PLL can clean up jitter on the 10 MHz
reference.

A very vague explanation. You are using a 1 ps accurate rifle to hit a
target that is moving around by 10's of ps. Then you want to determine
where the target is by watching the rifle.

I think you can have a rifle that is not so good as 1 ps and still get
the same result. It all runs through the same filter.

--

Rick

 

[Gerhard Hoffmann]

Am 15.09.2014 um 01:00 schrieb John Larkin:

I was thinking of doing something like that with a bunch of jfets.
BF862's have about 800 pV/rthz voltage noise and very low current
noise. Less propensity to rectify RF, too.

Someone has done this with 32 BF862. Each group of 4 needs a ferrite
bead against. osc.
I have once used 2 * 8 2SK-something in front of a ad797. That was
quite unstable: 1/f of the FETs, thermal drift, not much supply
suppression because of balance. FETs are all individuals.

With the averaged op amps, the input pairs are at least on the
same chip.

cheers, Gerhard

 

[Phil Hobbs]

On 9/14/2014 6:59 PM, rickman wrote:

On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John specifically said that you needed to drive the DFF differentially
to get the good jitter numbers, so despite having CLK and /CLK pins,
there's nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output into D
and clock it with the undivided signal.

BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing anything
so idiotic.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[Dimitrij Klingbeil]

On 15.09.2014 01:02, rickman wrote:

On 9/14/2014 3:49 PM, John Larkin wrote:
On Sun, 14 Sep 2014 15:22:10 -0400, rickman <gnuarm@gmail.com
wrote:

To fire things on time. My PLL can clean up jitter on the 10 MHz
reference.

A very vague explanation. You are using a 1 ps accurate rifle to
hit a target that is moving around by 10's of ps. Then you want to
determine where the target is by watching the rifle.

I think you can have a rifle that is not so good as 1 ps and still
get the same result. It all runs through the same filter.

Well, John did not say what exactly he's trying to fire, but it looks
like he means the "rifle" with the 500 TW. That's a highly distributed
"rifle" with 192 "chambers" being fired synchronously. John's probably
building the "mechanism" responsible for the action of each "pin".

(John, correct me if I'm wrong ...)

The one thing that strikes me as really odd, is that they want the thing
to be synchronized to a 10MHz signal over coax lines. The use of a
higher frequency and fiber optics would likely provide a much better
distribution of the timing signal.

Maybe John should consider running his own ovenized "master oscillator"
at a suitable (higher) frequency and PLLing it to the incoming 10 MHz
with a very long time constant (some people on the well-known Time Nuts
mailing list temperature-stabilize the ovens of their own GPSDOs to
millikelvins and then run the PLLs with filter time constants on the
order of hours or even days in order to keep ADEV as low as they can,
but then they only have a PPS signal to start from). Having 10 MHz to
start from is obviously much better than 1 PPS, so there's no need for
hours or days of PLL stabilization time, but still, using a more short
term stable (translate: less jittery) internal reference is probably
something to consider, before starting to synthesize the 155 MHz.

Regards
Dimitrij

 

[rickman]

On 9/14/2014 8:02 PM, Phil Hobbs wrote:

On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe. John
specifically said that you needed to drive the DFF differentially to get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

If you reclock the divided signal there will be tons of delay in even an
ECL FF.

--

Rick

 

[Phil Hobbs]

On 9/14/2014 8:42 PM, rickman wrote:

On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe. John
specifically said that you needed to drive the DFF differentially to get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.

If you reclock the divided signal there will be tons of delay in even an
ECL FF.

Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[josephkk]

On Sun, 14 Sep 2014 17:53:42 -0400, Phil Hobbs <hobbs@electrooptical.net>
wrote:

Frequency locking isn't difficult. Time locking to picoseconds is.
http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

Won't LC tanks have horrendous temperature coefficients?

Not that bad after all. Assuming a LC Q-factor of 100, you will have a
1 % -3 dB bandwidth. That would allow a 10000 ppm drift across the
temperature range (100 ppm/C across 100 C). After all, you are
interested in the harmonics of the crystal oscillator, not the filter
performance.

In the words of Rudyard Kipling, "Not so, but far otherwise." For a
single section the phase shift across the width of the resonance is on
the order of 1 radian, so in terms of phase, a filter with a Q of 100
magnifies the component tempcos by roughly 100 times. A time shift of 1
ps is about a milliradian at 155 MHz. Typical inductor tempcos of +100
ppm/C will give you a phase shift of something like

dPhi/dT ~ Q * dL/dT

or 0.01 radian/K, i.e. 10 ps/K.

Cheers

Phil Hobbs

I am not so sure about that. It seems to me that you have used native LC
tank phase noise when a forcing function version is more appropriate.

?-)

 

[rickman]

On 9/14/2014 8:49 PM, Phil Hobbs wrote:

On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe. John
specifically said that you needed to drive the DFF differentially to get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.

--

Rick

 

[Phil Hobbs]

On 9/14/2014 8:53 PM, josephkk wrote:

On Sun, 14 Sep 2014 17:53:42 -0400, Phil Hobbs <hobbs@electrooptical.net
wrote:


Frequency locking isn't difficult. Time locking to picoseconds is.
http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

Won't LC tanks have horrendous temperature coefficients?

Not that bad after all. Assuming a LC Q-factor of 100, you will have a
1 % -3 dB bandwidth. That would allow a 10000 ppm drift across the
temperature range (100 ppm/C across 100 C). After all, you are
interested in the harmonics of the crystal oscillator, not the filter
performance.

In the words of Rudyard Kipling, "Not so, but far otherwise." For a
single section the phase shift across the width of the resonance is on
the order of 1 radian, so in terms of phase, a filter with a Q of 100
magnifies the component tempcos by roughly 100 times. A time shift of 1
ps is about a milliradian at 155 MHz. Typical inductor tempcos of +100
ppm/C will give you a phase shift of something like

dPhi/dT ~ Q * dL/dT

or 0.01 radian/K, i.e. 10 ps/K.

Cheers

Phil Hobbs

I am not so sure about that. It seems to me that you have used native LC
tank phase noise when a forcing function version is more appropriate.

?-)


How so? I didn't mention phase noise, just tempco.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

Gerhard Hoffmann <ghf@hoffmann-hochfrequenz.de> wrote:
> <http://www.hoffmann-hochfrequenz.de/downloads/NoiseMeasurementsOnChemicalBatteries.pdf>

Cool!

It might be interesting to try something like an SLA/AGM battery
(Bleiakku), as found in computer UPSes, emergency lights, and so on. I
bet the good ones would do about as well as the NiCd cells you tested.

It's not yet accesible from the rest of the website, you must know
the exact address since I'm not yet happy with the results.

Would the material/plating of the battery holder contacts affect the
amount of noise you get? You might be making a thermocouple, or another
little battery, at the connections.

Matt Roberds

 

[John Larkin]

On Sun, 14 Sep 2014 20:42:17 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe. John
specifically said that you needed to drive the DFF differentially to get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

If you reclock the divided signal there will be tons of delay in even an
ECL FF.

A 10EP52 does not have an enable input.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[rickman]

On 9/14/2014 9:14 PM, John Larkin wrote:

On Sun, 14 Sep 2014 20:42:17 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe. John
specifically said that you needed to drive the DFF differentially to get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

If you reclock the divided signal there will be tons of delay in even an
ECL FF.

A 10EP52 does not have an enable input.

How do you plan to use the divided 80 kHz signal?

--

Rick

 

[Phil Hobbs]

On 9/14/2014 8:56 PM, rickman wrote:

On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John
specifically said that you needed to drive the DFF differentially to
get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output
into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.

*----------------<----------------------------------------*
| |
VCXO *-----* *-----* *-------* |
155.52 MHz ->-- /1944 ->-|D Q|------|D Q|---| LOOP |----*
| | | | | |FILTER |
V *--^--* *--^--* *-------*
| | |
*------->-------* *---<----10MHz REF
Resynch B-B phase det

With maybe a second DFF stage between the phase detector and the loop
filter, to get rid of any noise caused by metastability.

Cheers

Phil Hobbs
--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC
Optics, Electro-optics, Photonics, Analog Electronics

160 North State Road #203
Briarcliff Manor NY 10510

hobbs at electrooptical dot net
http://electrooptical.net

 

[John Larkin]

On Sun, 14 Sep 2014 20:56:34 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe. John
specifically said that you needed to drive the DFF differentially to get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.

About like this:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/BangBang_PLL.JPG



--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[Tom Miller]

"John Larkin" <jlarkin@highlandtechnology.com> wrote in message
news:j8gc1a9n6pq14t5jr17lbmlp38jma1n3ri@4ax.com...

On Sun, 14 Sep 2014 20:56:34 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John
specifically said that you needed to drive the DFF differentially to
get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output into
D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an
enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in even
an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.

About like this:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/BangBang_PLL.JPG



--

What is the 1 PPS for? I must have missed that message.

 

[rickman]

On 9/14/2014 9:30 PM, John Larkin wrote:

On Sun, 14 Sep 2014 20:56:34 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe. John
specifically said that you needed to drive the DFF differentially to get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.

About like this:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/BangBang_PLL.JPG

So where is the output?

--

Rick

 

[rickman]

On 9/14/2014 9:41 PM, Phil Hobbs wrote:

On 9/14/2014 8:56 PM, rickman wrote:
On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe.
John
specifically said that you needed to drive the DFF differentially to
get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output
into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing
anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an
enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in
even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.



*----------------<----------------------------------------*
| |
VCXO *-----* *-----* *-------* |
155.52 MHz ->-- /1944 ->-|D Q|------|D Q|---| LOOP |----*
| | | | | |FILTER |
V *--^--* *--^--* *-------*
| | |
*------->-------* *---<----10MHz REF
Resynch B-B phase det

With maybe a second DFF stage between the phase detector and the loop
filter, to get rid of any noise caused by metastability.

Where is the output?

--

Rick

 

[John Larkin]

On Sun, 14 Sep 2014 23:29:59 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 9:30 PM, John Larkin wrote:
On Sun, 14 Sep 2014 20:56:34 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe. John
specifically said that you needed to drive the DFF differentially to get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.

About like this:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/BangBang_PLL.JPG

So where is the output?

Wherever I need it to be. What a PITA you are.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[rickman]

On 9/14/2014 11:58 PM, John Larkin wrote:

On Sun, 14 Sep 2014 23:29:59 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 9:30 PM, John Larkin wrote:
On Sun, 14 Sep 2014 20:56:34 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/14/2014 8:49 PM, Phil Hobbs wrote:
On 9/14/2014 8:42 PM, rickman wrote:
On 9/14/2014 8:02 PM, Phil Hobbs wrote:
On 9/14/2014 6:59 PM, rickman wrote:
On 9/14/2014 5:32 PM, Phil Hobbs wrote:

Acquisition aids are a separate problem. I was talking about
*resynchronizing*, which is important here in two ways. First, the
jitter from the divide-by-1944 circuit has to be eliminated.

Why do you not understand that the jitter and delay of the divided
clock
is not an issue? It is not being used to clock anything. It is only
being used to isolate the actual clock edges by enabling the FF. It
only has to meet setup and hold times.

Packaged D-flops rarely come with clock enable pins in my universe. John
specifically said that you needed to drive the DFF differentially to get
the good jitter numbers, so despite having CLK and /CLK pins, there's
nothing to use as a clock enable.

The usual method for resynchronizing is to put the divider output into D
and clock it with the undivided signal.


BTW, the FF has to be clocked by the same clock that is being divided
down. Otherwise you get 1 full clock cycle of jitter in the enable
when
you sync it to the other clock.

Doing that would break the PLL, so I'm obviously not proposing anything
so idiotic.

How would that break the PLL? The reference clock is sampled by the D
input clocked by the VCXO clock. The divided signal has to be an enable
on the FF or it won't work because of the inherent delays in generating
the divided signal.

Nonsense. It just has to observe the setup and hold times.


If you reclock the divided signal there will be tons of delay in even an
ECL FF.


Putting a DFF on the counter output and clocking it with the 10 MHz
makes a crappy bang-bang phase detector, not a resynchronizer.

I have no idea what you are talking about. You seem to have a very
different picture of what the correct circuit is than I do. I think we
are not talking about the same circuits.

About like this:

https://dl.dropboxusercontent.com/u/53724080/Circuits/Oscillators/BangBang_PLL.JPG

So where is the output?

Wherever I need it to be. What a PITA you are.

By using the divided clock to clock the reference you have added an
unspecified delay which will vary with time, temperature, process and
voltage. Is all this going to give you the 1 ps spec you need? Is
there really no part available with an enable? That gets around the
problem totally.

I realize now that whenever you get pushed into having to deal with
problems you get angry and start insulting people. I'm sure that gets
you miles with your coworkers.

I realize now why others have said this may stable in frequency but you
can expect difficulties in phase. Or are you going to hand calibrate
each one for the particular 10EP52 you use?

--

Rick