PLL tricks

[Gerhard Hoffmann]

Am 14.09.2014 um 11:00 schrieb Bill Sloman:

On Sunday, 14 September 2014 16:58:17 UTC+10, Kevin Aylward wrote:
"John Larkin" wrote in message
news:1h291ahulit12anamhhlu27hrapque4mai@4ax.com...

snip

My box will receive a 10 MHz reference from the customer, from some
expensive Symmetrix GPS-disciplined thing. I'll also get a 1 PPS pulse
from that, and time-of-day data over Ethernet. It's my job to make
OC3-like optical data frames, at 155.52 MHz, that are exact in real
time to picoseconds.

Frequency locking isn't difficult. Time locking to picoseconds is.

http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf

looks like you need 2-way time transfer via DLLs and pseudo noise.
My current customer does just that from ground to space & back.

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

PLL are useful when you want programmability in frequency and no inductors,
but 80 year old LC tank technology blows PLL away in terms of noise
performance. For example, meeting -150 dBc (30fs jitter) flat band phase
noise at 2.5GHz is, essentially, not achievable with PLL techniques, not
that I am giving anything away on one of my current projects...

http://cds.linear.com/docs/en/datasheet/6948f.pdf

shows only -100dBc/Hz on its performance curves.

???
on page 8 I see the 3 and 4 GHz units break the -150 dBc/Hz
at 10 MHz offset, still linearly sinking towards the flat
noise floor.

Gerhard

 

[Bill Sloman]

On Sunday, 14 September 2014 22:19:24 UTC+10, Mike Perkins wrote:

On 14/09/2014 09:10, Bill Sloman wrote:

snip

John does claim to have avoided metastability, so he presumably has
done something equally clever. One can't entirely discount the
possibility that he's fooling himself, but it's kinder to give him
the benefit or the doubt.

I feel you haven't understood what John is trying to do.

I'm fairly sure that I understand that.

He wants metastability, but in a controlled way that he claims he gets
with these device.

That's what he's presumably getting though he initially denied it.

Where the output goes essentially from logic 0 to
logic 1 depending on whether these clocks are early or late by 1ps in a
gradual and monotonic manner.

They may, but the manufacturer doesn't guarantee their behaviour if you don't conform to the set-up and hold specifications, which does mean that what works with today's devices may not work after the manufacturer has tweaked the process.

In effect a phase detector with a huge gain. The output is analogue and
will be filtered before driving his VCXO.

John hopes that the output is "analog". It's certainly going to be filtered before it gets to the voltage drive that controls the phase (and - integrated - the frequency of the VXCO).

> My concern is that there will be so much other jitter in his system that it will never actually sit in this metastable region.

It wouldn't take much. The meta-stability window for ECLinPS is supposed to narrow.

He's used the same system - but clocked at 77MHz - to achieve a similar result with a different 155.52MHz clock, and the fact that he's not seen any metastability implies that what he's got does jiggle around enough.

--
Bill Sloman, Sydney

 

[Bill Sloman]

On Sunday, 14 September 2014 22:22:23 UTC+10, Mike Perkins wrote:

On 14/09/2014 07:58, Kevin Aylward wrote:

"John Larkin" wrote in message

news:1h291ahulit12anamhhlu27hrapque4mai@4ax.com...





Why not go out and buy a 9.7200MHz +/-10ppm crystal, and lock your

155.52MHz VCXO to that via a divide-by-sixteen counter?



You'll have to have your eight crystals ground to give exactly the right

frequencies, but there are small businesses that make a living out of

producing bespoke crystals.



Ahmmmm..... 155.52 Mhz is so bog standard that every xtal/oscillator

company

under the sun has xtals and oscillators in the golden range of 10MHz

to 50

Mhz that can be multiplied exactly up. e.g. 38.88Mhz and 19.44MHz. I

know,

because my company has then in stock, and my current asic design uses

them!



"19.44 MHz crystal" gets 2800 hits



I was going to suggest this right off the bat, but assumed they was some

system reason why he cant do that.

My box will receive a 10 MHz reference from the customer, from some

expensive Symmetrix GPS-disciplined thing. I'll also get a 1 PPS pulse

from that, and time-of-day data over Ethernet. It's my job to make OC3-like optical data frames, at 155.52 MHz, that are exact in real time to picoseconds.

Frequency locking isn't difficult. Time locking to picoseconds is.

http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

Won't LC tanks have horrendous temperature coefficients?

It would be varactor-tuned, or you might be able to find one of the old YIG-tuned microwave oscillators, to lock the whole system back to the external 10MHz clock.

--
Bill Sloman, Sydney

 

[Mike Perkins]

On 14/09/2014 09:10, Bill Sloman wrote:

<snip>

John does claim to have avoided metastability, so he presumably has
done something equally clever. One can't entirely discount the
possibility that he's fooling himself, but it's kinder to give him
the benefit or the doubt.

I feel you haven't understood what John is trying to do.

He wants metastability, but in a controlled way that he claims he gets
with these device. Where the output goes essentially from logic 0 to
logic 1 depending on whether these clocks are early or late by 1ps in a
gradual and monotonic manner.

In effect a phase detector with a huge gain. The output is analogue and
will be filtered before driving his VCXO.

My concern is that there will be so much other jitter in his system that
it will never actually sit in this metastable region.

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

 

[Mike Perkins]

On 14/09/2014 07:58, Kevin Aylward wrote:

"John Larkin" wrote in message
news:1h291ahulit12anamhhlu27hrapque4mai@4ax.com...


Why not go out and buy a 9.7200MHz +/-10ppm crystal, and lock your
155.52MHz VCXO to that via a divide-by-sixteen counter?

You'll have to have your eight crystals ground to give exactly the right
frequencies, but there are small businesses that make a living out of
producing bespoke crystals.

Ahmmmm..... 155.52 Mhz is so bog standard that every xtal/oscillator
company
under the sun has xtals and oscillators in the golden range of 10MHz
to 50
Mhz that can be multiplied exactly up. e.g. 38.88Mhz and 19.44MHz. I
know,
because my company has then in stock, and my current asic design uses
them!

"19.44 MHz crystal" gets 2800 hits

I was going to suggest this right off the bat, but assumed they was some
system reason why he cant do that.
My box will receive a 10 MHz reference from the customer, from some
expensive Symmetrix GPS-disciplined thing. I'll also get a 1 PPS pulse
from that, and time-of-day data over Ethernet. It's my job to make
OC3-like optical data frames, at 155.52 MHz, that are exact in real
time to picoseconds.

Frequency locking isn't difficult. Time locking to picoseconds is.
http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

Won't LC tanks have horrendous temperature coefficients?

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

 

On Sun, 14 Sep 2014 13:22:23 +0100, Mike Perkins <spam@spam.com>
wrote:

Frequency locking isn't difficult. Time locking to picoseconds is.
http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

Won't LC tanks have horrendous temperature coefficients?

Not that bad after all. Assuming a LC Q-factor of 100, you will have a
1 % -3 dB bandwidth. That would allow a 10000 ppm drift across the
temperature range (100 ppm/C across 100 C). After all, you are
interested in the harmonics of the crystal oscillator, not the filter
performance.

A classical 2x push/pull doubler with some filtering will give quite
nice waveforms with good suppression of the fundamental. A class-C
tripler+LC (like some MAR-xx MMICs) can also be easily cascaded. 5x
and 7x multipliers would need quite a lot of high Q filtering, Thus
use a combination of 2x and 3x multipliers to make up the required
frequency. Trying to use some higher harmonics will usually require
use of some high-Q resonators, like cavity resonators.

 

[Mike Perkins]

On 14/09/2014 13:43, upsidedown@downunder.com wrote:

On Sun, 14 Sep 2014 13:22:23 +0100, Mike Perkins <spam@spam.com
wrote:

Frequency locking isn't difficult. Time locking to picoseconds is.
http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

Won't LC tanks have horrendous temperature coefficients?

Not that bad after all. Assuming a LC Q-factor of 100, you will have a
1 % -3 dB bandwidth. That would allow a 10000 ppm drift across the
temperature range (100 ppm/C across 100 C). After all, you are
interested in the harmonics of the crystal oscillator, not the filter
performance.

A classical 2x push/pull doubler with some filtering will give quite
nice waveforms with good suppression of the fundamental. A class-C
tripler+LC (like some MAR-xx MMICs) can also be easily cascaded. 5x
and 7x multipliers would need quite a lot of high Q filtering, Thus
use a combination of 2x and 3x multipliers to make up the required
frequency. Trying to use some higher harmonics will usually require
use of some high-Q resonators, like cavity resonators.

I can see how a tank circuit could help with short term cycle to cycle
jitter but not long term accuracy. John want ps accuracy which at 10MHz
is 10ppm. Your drift would swamp that. Give a Q of 100, this implies
your phase shift would be 100 x any component ppm drift.

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

 

[Mike Perkins]

On 14/09/2014 15:28, Bill Sloman wrote:

On Sunday, 14 September 2014 22:19:24 UTC+10, Mike Perkins wrote:
On 14/09/2014 09:10, Bill Sloman wrote:

snip

John does claim to have avoided metastability, so he presumably
has done something equally clever. One can't entirely discount
the possibility that he's fooling himself, but it's kinder to
give him the benefit or the doubt.

I feel you haven't understood what John is trying to do.

I'm fairly sure that I understand that.

He wants metastability, but in a controlled way that he claims he
gets with these device.

That's what he's presumably getting though he initially denied it.

Where the output goes essentially from logic 0 to logic 1 depending
on whether these clocks are early or late by 1ps in a gradual and
monotonic manner.

They may, but the manufacturer doesn't guarantee their behaviour if
you don't conform to the set-up and hold specifications, which does
mean that what works with today's devices may not work after the
manufacturer has tweaked the process.

In effect a phase detector with a huge gain. The output is
analogue and will be filtered before driving his VCXO.

John hopes that the output is "analog". It's certainly going to be
filtered before it gets to the voltage drive that controls the phase
(and - integrated - the frequency of the VXCO).

My concern is that there will be so much other jitter in his system
that it will never actually sit in this metastable region.

It wouldn't take much. The meta-stability window for ECLinPS is
supposed to narrow.

He's used the same system - but clocked at 77MHz - to achieve a
similar result with a different 155.52MHz clock, and the fact that
he's not seen any metastability implies that what he's got does
jiggle around enough.

Without seeing the waveforms I have no idea.

What John is trying to do is make a clocked Sample/Hold using a
flip-flop. Sampling the rising edge of the divided clock, rather than a
true bang-gang phase detector.

As you say John would be dependant on a feature that isn't guaranteed by
the manufacturer, where a small change in process might have
consequences, such as introducing hysteresis.

I think a ps sample and hold circuit using a ring diode or similar would
be be more reliable, where the rising edge of divided clock can be
sampled to produce an analogue output dependant on relative phase. Gain
and loop stability/accuracy could then be analysed.

I'd also want the whole circuit temperature stabilised!

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

 

On Sun, 14 Sep 2014 14:34:29 +0100, Mike Perkins <spam@spam.com>
wrote:

On 14/09/2014 13:43, upsidedown@downunder.com wrote:
On Sun, 14 Sep 2014 13:22:23 +0100, Mike Perkins <spam@spam.com
wrote:

Frequency locking isn't difficult. Time locking to picoseconds is.
http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

Won't LC tanks have horrendous temperature coefficients?

Not that bad after all. Assuming a LC Q-factor of 100, you will have a
1 % -3 dB bandwidth. That would allow a 10000 ppm drift across the
temperature range (100 ppm/C across 100 C). After all, you are
interested in the harmonics of the crystal oscillator, not the filter
performance.

A classical 2x push/pull doubler with some filtering will give quite
nice waveforms with good suppression of the fundamental. A class-C
tripler+LC (like some MAR-xx MMICs) can also be easily cascaded. 5x
and 7x multipliers would need quite a lot of high Q filtering, Thus
use a combination of 2x and 3x multipliers to make up the required
frequency. Trying to use some higher harmonics will usually require
use of some high-Q resonators, like cavity resonators.

I can see how a tank circuit could help with short term cycle to cycle
jitter but not long term accuracy. John want ps accuracy which at 10MHz
is 10ppm. Your drift would swamp that. Give a Q of 100, this implies
your phase shift would be 100 x any component ppm drift.

In a classical frequency multiplier, such as an overdriven amplifier
converting a sine wave to square wave and the LC is simply used to
select the required harmonics. For a tripler, should take out the
fundamental and 5th and higher order odd harmonics. the required
attenuation determines the required Q.

A push pull doubler is nice, since it effectively removes the
fundamental and the filtering only needs to remove the 4th and higher
even harmonics, with low Q filtering.

 

[Kevin Aylward]

"Mike Perkins" wrote in message
newsJudnSUMALP-BIjJnZ2dnUVZ8tKdnZ2d@bt.com...

On 14/09/2014 13:43, upsidedown@downunder.com wrote:

On Sun, 14 Sep 2014 13:22:23 +0100, Mike Perkins <spam@spam.com
wrote:

Frequency locking isn't difficult. Time locking to picoseconds is.
http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

Won't LC tanks have horrendous temperature coefficients?

Not that bad after all. Assuming a LC Q-factor of 100, you will have a
1 % -3 dB bandwidth. That would allow a 10000 ppm drift across the
temperature range (100 ppm/C across 100 C). After all, you are
interested in the harmonics of the crystal oscillator, not the filter
performance.

A classical 2x push/pull doubler with some filtering will give quite
nice waveforms with good suppression of the fundamental. A class-C
tripler+LC (like some MAR-xx MMICs) can also be easily cascaded. 5x
and 7x multipliers would need quite a lot of high Q filtering, Thus
use a combination of 2x and 3x multipliers to make up the required
frequency. Trying to use some higher harmonics will usually require
use of some high-Q resonators, like cavity resonators.

I can see how a tank circuit could help with short term cycle to cycle
jitter but not long term accuracy. John want ps accuracy which at 10MHz is
10ppm. Your drift would swamp that. Give a Q of 100, this implies your
phase shift would be 100 x any component ppm drift.

The tank is not determining the frequency, the tank "locks" on to the input
clock, exactly. Tuning errors only really effect the sub harmonic rejection.
There is some some noise penalty, but not too significant.

I am just pointing out that tank multiplication gets lower noise than a PLL.
You still have the issues of getting the correct input frequency.

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

[Kevin Aylward]

"Gerhard Hoffmann" wrote in message
news:c7l84fFsqprU1@mid.individual.net...

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

PLL are useful when you want programmability in frequency and no
inductors,
but 80 year old LC tank technology blows PLL away in terms of noise
performance. For example, meeting -150 dBc (30fs jitter) flat band phase
noise at 2.5GHz is, essentially, not achievable with PLL techniques, not
that I am giving anything away on one of my current projects...

http://cds.linear.com/docs/en/datasheet/6948f.pdf

shows only -100dBc/Hz on its performance curves.

???
on page 8 I see the 3 and 4 GHz units break the -150 dBc/Hz
at 10 MHz offset, still linearly sinking towards the flat
noise floor.

Ah... I should add... flat band noise with a multiplication of times 9.
Multiplying up has an inherent theoretical noise increase of 20.log(mult
ratio), so a times 9 is going to increase the basic oscillator phase noise
by around 20dB, irrespective of any added noise of the processing. This
means the oscillator noise floor needs better than -170dBc to get -150dBc
out. This is actually quite difficult at a xtal osc frequency of 277Mhz.

At the moment, I have not assimilated what the graphs and data sheet in
6948f.pdf mean. Like, what is the input frequency and what is the output
frequency. It looks like there are Fin=Fout in the graph and some lower
ration in the tables.

Kevin Aylward
www.kevinaylward.co.uk
www.anasoft.co.uk - SuperSpice

 

[Mike Perkins]

On 14/09/2014 18:37, Kevin Aylward wrote:

"Mike Perkins" wrote in message
newsJudnSUMALP-BIjJnZ2dnUVZ8tKdnZ2d@bt.com...

On 14/09/2014 13:43, upsidedown@downunder.com wrote:
On Sun, 14 Sep 2014 13:22:23 +0100, Mike Perkins <spam@spam.com
wrote:

Frequency locking isn't difficult. Time locking to picoseconds is.
http://www.slac.stanford.edu/econf/C011127/TUAP069.pdf

What I will say though, is multiplying up by harmonic selection from LC
tanks gives orders of lower phase noise/jitter than a PLL.

Won't LC tanks have horrendous temperature coefficients?

Not that bad after all. Assuming a LC Q-factor of 100, you will have a
1 % -3 dB bandwidth. That would allow a 10000 ppm drift across the
temperature range (100 ppm/C across 100 C). After all, you are
interested in the harmonics of the crystal oscillator, not the filter
performance.

A classical 2x push/pull doubler with some filtering will give quite
nice waveforms with good suppression of the fundamental. A class-C
tripler+LC (like some MAR-xx MMICs) can also be easily cascaded. 5x
and 7x multipliers would need quite a lot of high Q filtering, Thus
use a combination of 2x and 3x multipliers to make up the required
frequency. Trying to use some higher harmonics will usually require
use of some high-Q resonators, like cavity resonators.

I can see how a tank circuit could help with short term cycle to cycle
jitter but not long term accuracy. John want ps accuracy which at
10MHz is 10ppm. Your drift would swamp that. Give a Q of 100, this
implies your phase shift would be 100 x any component ppm drift.

The tank is not determining the frequency, the tank "locks" on to the
input clock, exactly. Tuning errors only really effect the sub harmonic
rejection. There is some some noise penalty, but not too significant.

I am just pointing out that tank multiplication gets lower noise than a
PLL. You still have the issues of getting the correct input frequency.

I was answering upsidedown's assertion that a high of 100 would be
advantageous, where my immediate thought was it would be disastrous for
long term stability.

Any analogue filtering will still have an effect around the frequency of
interest, and so induce a phase dependent on temperature and to a lesser
extent on ageing.

I don't feel maintaining waveform relationships to ps accuracy will be
practical here using analogue filtering that is only an octave or two
away from the fundamental.

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

 

[John Larkin]

On Sun, 14 Sep 2014 00:58:22 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/13/2014 10:57 PM, Gerhard Hoffmann wrote:
Am 14.09.2014 um 02:48 schrieb rickman:
On 9/10/2014 4:54 AM, Gerhard Hoffmann wrote:
Am 10.09.2014 um 01:54 schrieb John Larkin:

I could DDS the 155.52 down to 10 MHz, and phase detect at 10 MHz, but
that sounds jitterey to me, and it looks like I can't hit the exact
frequency ratio anyhow.

Dividing EXACTLY with a DDS can be surprisingly hard, one could
find that one is always off by 2e-32 or 2e-48 or whatever
but one is never exactly on the spot, never really synchronous.

That is only true if you don't control both your step size and your
modulus. No one ever said you had to use 2^n as a modulus.

You have snipped too much context. I was the first to propose
just that, and that my sin/cos function on opencores.org
would be easy to adopt. There even are some TODOs in the VHDL
source code already.

Once, there was a BCD coded DDS from Stanford IIRC that
could get it exact for ateasy-to-write decimal numbers.

Yes, they picked a modulus that worked for them.

exactly.


And I always see here "1 ps jitter" without any qualification.
That makes as much sense as "my car consumes 8 liters of Diesel".
From here to work? per 100 Km? One hefty accelleration?

Jitter needs measurement bandwidth. When I said that telecom ps
are easy, I meant exactly that. They start integrating their
phasenoise at 12 KHz or so. All of the 1/f region is therefore
ignored, and that is the lion's share.


A friend of mine had made systematic phase noise characterizations
when he built frequency synthesizers for avionics and found
that ECL in Mosaic 3 process was about the worst that industry
had to offer, noisewise.

I find it hard to believe that Mosaic's grand children
are suddenly on the other end of the scale. Along with the
ultrafast switching comes ultrawide noise bandwidth where one must
integrate over many harmonics from DC to daylight.

I'm not sure of all the ramifications of this, but I can tell you that
John is just looking at one aspect of the ECL circuit, the timing window
in which a transition on the input results in an uncertain output. This
is often called the metastable window. John is not worried about the
output being metastable. He is concerned by the fact that it would
"add" jitter to the sampling process.

Actually, I'm not concerned about that either. Metastability does not
affect the performance of the bang-bang phase detector.

ECL flops don't catch fire when they go metastable; their prop delay
just increases some. That wouldn't affect my phase detector; it
arguably improves it slightly.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[John Larkin]

On Sun, 14 Sep 2014 01:09:38 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/13/2014 11:17 PM, John Larkin wrote:
On Sat, 13 Sep 2014 23:00:03 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/13/2014 10:20 PM, John Larkin wrote:

On 14/09/2014 01:13, rickman wrote:
On 9/13/2014 7:34 PM, Phil Hobbs wrote:

Understood. Anecdotally, as I say, two stages of resynchronization
exhibit usefully less jitter than one. YMMV.

I believe Phil's point is that metastability is a problem no matter how
it is perceived. I don't think you can analyze this circuit to come up
with a number of MTBF of the synchronizer FF. John said in an earlier
post that 100's of ps of metastability won't be a problem, but the
nature of metastability is that you can't predict the duration. The
best you can hope for is to characterize the average frequency of
failure and in this case the feedback will be pushing the circuit to the
point of failure.

In fact, that is the difference between this circuit and one built to
test the metastability characteristics of a device... that circuit would
have a reproducible and defined distribution of the edges being
coincident while this one is hard to characterize and is actually trying
to maximize metastability.

Adding a second FF to reclock the output of the first *will* greatly
improve your MTBF and cost next to nothing relative to the rest of the
design. But then the impact of a failure may be insignificant. What
happens to the filtered output if the output of the FF is in a random
state or even oscillates for some time between the 80 kHz samples?

Metastability is not a problem for the dflop phase detector. Bring it
on!

You sound like you are off your meds again

Care to explain yourself? I wonder if you fully understand metastability.

The only time the dflop phase detector might go metastable is when the
VCO and reference edges are exactly aligned.

"Exactly"? What does that mean?

Circular definition: It means the the clock and data transition so
closely in time that the flop goes metastable, teasing the setup/hold
boundary within some number of femtoseconds.

There is no such thing as exact, only
>exact to within some spec.

I'm an engineer; I don't let philosophical arguments keep me from
building and selling stuff.

In this case this window is *exactly* the

source of your jitter isn't it? The input transitions at some close
time of the clock and instead of being always seen as a '1' is sometimes
seen as a '0'. Or is there another source of jitter having to do with
fluctuations in the timing of the internal circuit?

The ideal, noiseless bangbang PLL, with an integrator in the filter
path, will have the phase detector flop alternate 1/0 as the phase
alternates early/late, at successive sample shots. The dflop phase
alternation then sets the loop jitter. DC plus 40 KHz ripple into the
VCO.

But all real clocks have noise, so the PD flop output will in fact be
a stream of random binary bits, at 80K bps, that servo to 50% duty
cycle, with the rare metastability event. The binary noise stream gets
processed by the loop filter into a DC level with some noise spectrum,
and that goes into the VCO input of the 155 MHz VCXO.

Interesting loop. Sorta delta-sigma.

In that case, we don't
care whether the flop output goes to 1 or 0, so it may as well flail
around for a few ns. At 80 KHz, there's gobs of time for an ECL flop
to resolve.

I expect with all the filtering it may well not matter much. The 80 kHz
doesn't matter so much since you aren't clocking the output. The
filtering is what prevents it from affecting the VCCXO.


ECL flops resolve fast, and don't do stupid oscillatory stuff like old
TTL. 74LS could take many microseconds to settle, and would usually
oscillate to boot. Metastability events would make clicks on a nearby
FM radio.

What is different about the ECL stuff that it wouldn't oscillate? My
understanding is that the FF contains what amounts to a ring oscillator
if it is put into an unstable condition of a '1' on part of the circuit
and a '0' on another they chase each other around. Eventually one
catches up with the other and the oscillations stop since the circuit is
inherently stable.

ECL tends to have extended prop delay on metastability events, maybe a
plateau on the output edge, sometimes even a brief glitch in the wrong
(non-ultimate) direction. Of course, there are different parts and
families and manufacturers, but ECL in general doesn't do the
many-cycle oscillation that TTL tended to do; probably a consequence
of TTL being saturating logic and ECL being non-saturating. In my
application, it wouldn't matter anyhow. If the clock edges are that
well aligned, let it oscillate for a while.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[rickman]

On 9/14/2014 5:00 AM, Bill Sloman wrote:

On Sunday, 14 September 2014 13:17:17 UTC+10, John Larkin wrote:

The only time the dflop phase detector might go metastable is when the
VCO and reference edges are exactly aligned. In that case, we don't
care whether the flop output goes to 1 or 0, so it may as well flail
around for a few ns. At 80 KHz, there's gobs of time for an ECL flop
to resolve.

ECL flops resolve fast, and don't do stupid oscillatory stuff like old
TTL. 74LS could take many microseconds to settle, and would usually
oscillate to boot. Metastability events would make clicks on a nearby
FM radio.

But the circuit - as described - is deliberately designed to maximise the chance that the ECL bistable will go into a metastable state.

And, as I said, it doesn't matter anyhow.

So John is fooling himself. Presumably it happens rarely enough not to matter much, if his 77MHz to 155.52MHz synchroniser works.

John may be glossing over some aspects of what happens when ECL goes
metastable and how often it might happen, but I'm not convinced it will
be a problem when it does happen.

The normal output of the ECL FF will be a 1 or a 0 for 12.5 us at a
time. If the FF goes metastable it will either be in the wrong state or
will do some funny analog stuff like output an intermediate voltage or
even oscillate. Since the output is being treated as analog and
filtered, the worst case will be the wrong value for one sample period.
I have to assume the filter and gain will result in a minimal impact
from this. If the clock edges are so close the FF goes metastable which
polarity is "wrong" anyway?

The worst I can see is that the circuit won't let the phase cross the
boundary between positive and negative. Each time the phase delta gets
close to zero and metastability gives a "wrong" polarity it "bounces"
off the crossing and remains the same polarity. Not sure this is a
problem either.

Even if his argument is just waving his arms, I think John is right in
that metastability is not much of an issue.

--

Rick

 

[rickman]

On 9/14/2014 4:10 AM, Bill Sloman wrote:

On Sunday, 14 September 2014 13:08:01 UTC+10, rickman wrote:
On 9/13/2014 10:54 PM, Bill Sloman wrote:
1psec relative stability misses the point that dividing the
155.52MHz down to 80kHz introduces more than a 1psec of phase shift, as does dividing 10MHz down to 80kHz.

It produces zero ps of phase shift in the clocks because the divided
signal is not used to clock anything. It is used to *enable* the FF
that is clocked by one clock and samples the other clock on the D input.

John has said the 80 kHz will be resync'ed to the clock because it comes
from the FPGA with a considerable delay, but as long as that delay puts
it outside of the setup/hold window the delay has no bearing on the
circuit.

That needs thinking about. When I did a similar trick with TTL pulse stream and a 200MHz clock, the propagation delay from the original 200MHz clock was potentially quite a bit longer than 5nsec, and the difference between least delay and worst case delay was more than 5nsec, so I had to allow the user to pick the edge of the 200MHz clock that was furthest away from the actual TTL transitions.

FPGA's tend to be fast than TTL these days, and synchronous dividers using look-ahead carry can have minimal propagation delays from the clock, but 6.43 nsec doesn't give you a lot of propagation time. It's a little more than a metre of coax cable (shades of the faster than light neutrinos).

Yup, 155 MHz needs to be thought about, but it is not at all unusual and
is by no means a show stopper. Most likely the signal would need to be
clocked into a FF in the IO block to minimize delay and if that isn't
good enough it may require a PLL for the clock in the FPGA to offset the
output delays.

There is also the issue of getting from CMOS to ECL, but I'm sure that
isn't so hard to do with proper attention paid to the delays.

--

Rick

 

[John Larkin]

On Sun, 14 Sep 2014 15:49:51 +0100, Mike Perkins <spam@spam.com>
wrote:

On 14/09/2014 15:28, Bill Sloman wrote:
On Sunday, 14 September 2014 22:19:24 UTC+10, Mike Perkins wrote:
On 14/09/2014 09:10, Bill Sloman wrote:

snip

John does claim to have avoided metastability, so he presumably
has done something equally clever. One can't entirely discount
the possibility that he's fooling himself, but it's kinder to
give him the benefit or the doubt.

I feel you haven't understood what John is trying to do.

I'm fairly sure that I understand that.

He wants metastability, but in a controlled way that he claims he
gets with these device.

That's what he's presumably getting though he initially denied it.

Where the output goes essentially from logic 0 to logic 1 depending
on whether these clocks are early or late by 1ps in a gradual and
monotonic manner.

They may, but the manufacturer doesn't guarantee their behaviour if
you don't conform to the set-up and hold specifications, which does
mean that what works with today's devices may not work after the
manufacturer has tweaked the process.

In effect a phase detector with a huge gain. The output is
analogue and will be filtered before driving his VCXO.

John hopes that the output is "analog". It's certainly going to be
filtered before it gets to the voltage drive that controls the phase
(and - integrated - the frequency of the VXCO).

My concern is that there will be so much other jitter in his system
that it will never actually sit in this metastable region.

It wouldn't take much. The meta-stability window for ECLinPS is
supposed to narrow.

He's used the same system - but clocked at 77MHz - to achieve a
similar result with a different 155.52MHz clock, and the fact that
he's not seen any metastability implies that what he's got does
jiggle around enough.

Without seeing the waveforms I have no idea.

What John is trying to do is make a clocked Sample/Hold using a
flip-flop. Sampling the rising edge of the divided clock, rather than a
true bang-gang phase detector.

Am I? Gosh, I didn't know that.

As you say John would be dependant on a feature that isn't guaranteed by
the manufacturer, where a small change in process might have
consequences, such as introducing hysteresis.

I have observed setup/hold hysteresis in 10H-series ECL flops, on the
order of a few ps, but I haven't measured it in the EclipsLite or
EclipsPlus parts. It's not an easy measurement to set up.

Since I can expect several, maybe 10's of, ps of RMS jitter on my 10
MHz reference (or I can add it, if I want to) a little time hysteresis
wouldn't affect my loop much.

I think a ps sample and hold circuit using a ring diode or similar would
be be more reliable, where the rising edge of divided clock can be
sampled to produce an analogue output dependant on relative phase. Gain
and loop stability/accuracy could then be analysed.

I'd also want the whole circuit temperature stabilised!

It would need to be, if I used an analog s/h. The ECL flops, with
differential data and clock inputs, are impressively stable with
temperature. I've done this before, at 77 MHz sample rate, and got the
entire instrument below 1 ps per degree C, with a bit of overall TC
compensation.


--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

 

[rickman]

On 9/14/2014 8:19 AM, Mike Perkins wrote:

On 14/09/2014 09:10, Bill Sloman wrote:

snip

John does claim to have avoided metastability, so he presumably has
done something equally clever. One can't entirely discount the
possibility that he's fooling himself, but it's kinder to give him
the benefit or the doubt.

I feel you haven't understood what John is trying to do.

He wants metastability, but in a controlled way that he claims he gets
with these device. Where the output goes essentially from logic 0 to
logic 1 depending on whether these clocks are early or late by 1ps in a
gradual and monotonic manner.

That is an important point. Metastability will have a *major* impact on
the *monotonicity* of the phase detector. If he wants to keep the two
clocks to within 1 ps and the metastable window is 1 ps, he is doomed.
Instead of being monotonic the phase detector may end up a random bit
generator. This depends on the details of the window size and the
behavior within that window. Normally metastable behavior is considered
to be chaotic, not monotonic.

--

Rick

 

[rickman]

On 9/14/2014 2:59 PM, John Larkin wrote:

On Sun, 14 Sep 2014 01:09:38 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/13/2014 11:17 PM, John Larkin wrote:
On Sat, 13 Sep 2014 23:00:03 -0400, rickman <gnuarm@gmail.com> wrote:

On 9/13/2014 10:20 PM, John Larkin wrote:

On 14/09/2014 01:13, rickman wrote:
On 9/13/2014 7:34 PM, Phil Hobbs wrote:

Understood. Anecdotally, as I say, two stages of resynchronization
exhibit usefully less jitter than one. YMMV.

I believe Phil's point is that metastability is a problem no matter how
it is perceived. I don't think you can analyze this circuit to come up
with a number of MTBF of the synchronizer FF. John said in an earlier
post that 100's of ps of metastability won't be a problem, but the
nature of metastability is that you can't predict the duration. The
best you can hope for is to characterize the average frequency of
failure and in this case the feedback will be pushing the circuit to the
point of failure.

In fact, that is the difference between this circuit and one built to
test the metastability characteristics of a device... that circuit would
have a reproducible and defined distribution of the edges being
coincident while this one is hard to characterize and is actually trying
to maximize metastability.

Adding a second FF to reclock the output of the first *will* greatly
improve your MTBF and cost next to nothing relative to the rest of the
design. But then the impact of a failure may be insignificant. What
happens to the filtered output if the output of the FF is in a random
state or even oscillates for some time between the 80 kHz samples?

Metastability is not a problem for the dflop phase detector. Bring it
on!

You sound like you are off your meds again

Care to explain yourself? I wonder if you fully understand metastability.

The only time the dflop phase detector might go metastable is when the
VCO and reference edges are exactly aligned.

"Exactly"? What does that mean?

Circular definition: It means the the clock and data transition so
closely in time that the flop goes metastable, teasing the setup/hold
boundary within some number of femtoseconds.

Ok, yes, that is a circular definition. The circuit will go metastable
when the clock edges are close enough to cause metastability. Duh!

Where did you get the femtoseconds number? I thought elsewhere you said
the metastable window was 1 ps??? This is a very important aspect of
proper operation. If this window is large it will greatly increase the
noise of the PD output even at very low frequencies below your filter
cutoff.

There is no such thing as exact, only
exact to within some spec.

I'm an engineer; I don't let philosophical arguments keep me from
building and selling stuff.

Yes, I know, you build lots of stuff, you are just poor at discussing it
in technical terms.

In this case this window is *exactly* the
source of your jitter isn't it? The input transitions at some close
time of the clock and instead of being always seen as a '1' is sometimes
seen as a '0'. Or is there another source of jitter having to do with
fluctuations in the timing of the internal circuit?

The ideal, noiseless bangbang PLL, with an integrator in the filter
path, will have the phase detector flop alternate 1/0 as the phase
alternates early/late, at successive sample shots. The dflop phase
alternation then sets the loop jitter. DC plus 40 KHz ripple into the
VCO.

But all real clocks have noise, so the PD flop output will in fact be
a stream of random binary bits, at 80K bps, that servo to 50% duty
cycle, with the rare metastability event. The binary noise stream gets
processed by the loop filter into a DC level with some noise spectrum,
and that goes into the VCO input of the 155 MHz VCXO.

But the metastable may not be so rare. It pushes the VCXO in the
opposite direction you want it to go.

Interesting loop. Sorta delta-sigma.




In that case, we don't
care whether the flop output goes to 1 or 0, so it may as well flail
around for a few ns. At 80 KHz, there's gobs of time for an ECL flop
to resolve.

I expect with all the filtering it may well not matter much. The 80 kHz
doesn't matter so much since you aren't clocking the output. The
filtering is what prevents it from affecting the VCCXO.


ECL flops resolve fast, and don't do stupid oscillatory stuff like old
TTL. 74LS could take many microseconds to settle, and would usually
oscillate to boot. Metastability events would make clicks on a nearby
FM radio.

What is different about the ECL stuff that it wouldn't oscillate? My
understanding is that the FF contains what amounts to a ring oscillator
if it is put into an unstable condition of a '1' on part of the circuit
and a '0' on another they chase each other around. Eventually one
catches up with the other and the oscillations stop since the circuit is
inherently stable.

ECL tends to have extended prop delay on metastability events, maybe a
plateau on the output edge, sometimes even a brief glitch in the wrong
(non-ultimate) direction. Of course, there are different parts and
families and manufacturers, but ECL in general doesn't do the
many-cycle oscillation that TTL tended to do; probably a consequence
of TTL being saturating logic and ECL being non-saturating. In my
application, it wouldn't matter anyhow. If the clock edges are that
well aligned, let it oscillate for a while.

"In general"? So it does oscillate. TTL doesn't *tend* to oscillate,
but it will.

--

Rick

 

[John Larkin]

On Sun, 14 Sep 2014 08:41:05 GMT, Jan Panteltje <panteltje@yahoo.com>
wrote:

On a sunny day (Sat, 13 Sep 2014 14:28:39 -0700) it happened John Larkin
jlarkin@highlandtechnology.com> wrote in
44d91adte3vc7jipnapet6okglevfn40qm@4ax.com>:

You can't do any better than the phase comparator. So I can see why he
want's that as good as possible. But the delays introduced *after* the
phase comparator will not produce phase errors. That delay is only of
consequence to the loop stability.

Right. The dflop phase detector has such high equivalent gain that the
downstream lowpass won't add significant time error.

John, I was thinking last night about this problem,
but I quickly, for the 1 ps jitter case, got curious about your 10 MHz reference.
For sure that needs to be 'better'.
Is it a sinewave? A symmetrical square wave? Rise times?

That's the scariest part of the problem. It will be a single-ended
(BNC, coax) 10 MHz sine wave from a GPS-disciplined source. I need to
bandpass filter it, to remove as much ground-loop-EMI crud as
possible, and zero-cross detect it with a fast ECL comparator. So the
BPF needs to have a super low prop delay temperature coefficient,
which will no doubt be interesting. I assume we'll have an ambient
temperature sensor on the PC board, and apply some sort of software
tweak to the overall delay, to null out most of the delay tempco.

The flip-flop phase comparators are noisy by themselves,
in precise nanosecond locking systems I have worked with, you first lock to
frequency with a simple phase comparator, and then after frequency lock
switch to a second more precise phase comparator, and sometimes even a third.
I have never done a pico second accurate lock.

Last time I did this, I had a switchable loop filter. The supervising
uP set it to wideband mode until it detected lock, then switched to
narrowband mode to optimize jitter. That works if both the reference
and the VCXO are pretty close to begin with.

Anyway after frequency lock you switch to the normal PID lock, I have used sample and hold
on a ramp for that, so you are in linear range and no 'bang bang' noise is present.
If the system is knocked out of lock, then you go back to frequency comparator etc.
For the PID case you can set gain and I and D compensation and you like.

--

John Larkin Highland Technology, Inc

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com