M
mehrdad.najibi@gmail.com
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We have Just made publicized the beta release of Persia, our academic
asynchronous synthesis tool. Persia is designed and implemented in
Amirkabir University asynchronous design group.
You can download its windows installation package from: www.asynchronous.ir
Persia ýis an asynchronous synthesis tool intended to provide an
automatic synthesis in the field of QDI ý(Quasi Delay Insensitive)
asynchronous circuits. The synthesis flow of Persia is based on
standard Verilog powered by READ-WRITE macros for behavioral high
level specification.
The design procedure in Persia starts with a high level specification
of the circuit in verilogCSP. After a functional preserving
decomposition, the sequential high level specification is transformed
into highly concurrent communicating processes which can be directly
mapped into pre-designed PCFB buffer templates.
Each PCFB template is implemented using a set of standard cells with
no special timing constraint between the cells. With no external
Isochronoic fork assumption so the physical design can be carried out
using standard layout tools.
The output of the Persia can be verified at every stage of synthesis
by a standard Verilog simulator.
We are pleased to received your comments on Persia.
asynchronous synthesis tool. Persia is designed and implemented in
Amirkabir University asynchronous design group.
You can download its windows installation package from: www.asynchronous.ir
Persia ýis an asynchronous synthesis tool intended to provide an
automatic synthesis in the field of QDI ý(Quasi Delay Insensitive)
asynchronous circuits. The synthesis flow of Persia is based on
standard Verilog powered by READ-WRITE macros for behavioral high
level specification.
The design procedure in Persia starts with a high level specification
of the circuit in verilogCSP. After a functional preserving
decomposition, the sequential high level specification is transformed
into highly concurrent communicating processes which can be directly
mapped into pre-designed PCFB buffer templates.
Each PCFB template is implemented using a set of standard cells with
no special timing constraint between the cells. With no external
Isochronoic fork assumption so the physical design can be carried out
using standard layout tools.
The output of the Persia can be verified at every stage of synthesis
by a standard Verilog simulator.
We are pleased to received your comments on Persia.