PCI Bus layout for "on board" design.

[Sylvain Munaut]

Hello,


I'd like to know what the considerations are for the PCB layout of a "internal" PCI bus.
By that, I mean I have the PCI Host bridge, arbiter and devices on a single embedded board.


Since they are all almost 'in line' I thought to make :



PCI PCI PCI
Dev 1 Dev 2 Dev 3 ....
||||| |||||| |||||
\================================\
\================================\
\================================\
||||||
PCI
Host


iow, "long" (not that long, 20 inch very max), horizontal traces for all the PCI signals,
on an inner signal layer, then all the traces to the chips (host or dev) would be on the
top layer and just 'via'ed direct to the bus. Of course, keep the trace withing the 60-100
ohm impedance range and with sufficient horizontal spacing (like 2-3 W). But I didn't
plan for any termination at either end (PCI don't need/want them I think).

Is it important the order of devices or to have the PCI host at one "end" of that bus ?

Another concern is that the CPU I use share some lines between PCI and other busses ...
(like IDE and local bus ...), what should I be aware of ?


Thanks for any insight,

Sylvain