No Transmission Gate in Standard Cell Library

[Henning Bahr]

Hi all,

I can't find any Transmission Gates in my ASIC standard cell library.
Is that common? If it's common, why aren't they included?

Cheers,
Henning

 

[Hooman]

Henning.Bahr@ncl.ac.uk (Henning Bahr) wrote in message news:<8679149d.0308190130.2c7c3859@posting.google.com>...

Hi all,

I can't find any Transmission Gates in my ASIC standard cell library.
Is that common? If it's common, why aren't they included?

Cheers,
Henning

Hi,

I have the same question. Why there is no TG in any standard cell
library and how it could be added to a library?

Regards
Hooman

 

[Muzaffer Kal]

On 9 Sep 2003 21:05:47 -0700, nhooman@eleceng.adelaide.edu.au (Hooman)
wrote:

Henning.Bahr@ncl.ac.uk (Henning Bahr) wrote in message news:<8679149d.0308190130.2c7c3859@posting.google.com>...
Hi all,

I can't find any Transmission Gates in my ASIC standard cell library.
Is that common? If it's common, why aren't they included?

Cheers,
Henning

Hi,

I have the same question. Why there is no TG in any standard cell
library and how it could be added to a library?

Regards
Hooman

Maybe you're not checking the right cell type. Look for a Tri-State
buffer in your library. Almost all standard cell libraries have
internal tri-state buffers. If your library doesn't include it, you
can design the cell yourself, do a LEF for it for P&R. You also need
to simulate it in spice to extract the timing values.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

 

[B]

Hooman wrote:

Henning.Bahr@ncl.ac.uk (Henning Bahr) wrote in message news:<8679149d.0308190130.2c7c3859@posting.google.com>...

Hi all,

I can't find any Transmission Gates in my ASIC standard cell library.
Is that common? If it's common, why aren't they included?

Cheers,
Henning


Hi,

I have the same question. Why there is no TG in any standard cell
library and how it could be added to a library?

Regards
Hooman
This is the short answer

It's question of methodology of work.
SC lib : think of gates. Well characterized gates allow using
HDL/Synth/TA/PR.
TG means you're thinking transistors (and may be full custom?)
At your own risk, you can mix both styles and design at the
transistor level. But remember transistor level means you're
in Spice domain.