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Newbee in VHDL ... why is this not working?...

R

Rick C

Guest
On Friday, May 15, 2020 at 7:06:42 AM UTC-4, Christoph Linden wrote:
Am Freitag, 15. Mai 2020 09:02:59 UTC+2 schrieb Rick C:
On Friday, May 15, 2020 at 2:00:27 AM UTC-4, Christoph Linden wrote:
Am Freitag, 15. Mai 2020 00:46:01 UTC+2 schrieb Rick C:
Thank you Rick, very helpful.

1. Unfortunately I do not know anymore what the questions should have been. I believe it was in the ballpark how I can do this similar to a structural design but without defining single and gates.

2. The o_sum part. The problem is, that for whatever reason google.groups interpreted part of the code as \"quote\". So if you click on the quote you see, that it is actually two entities. One entity is calculating the carry look ahead and the other is doing the actual add of the four bits.

That is why it looks so weird if you do not unfold the quote.

But anyhow I understood what you was saying and yes, I just used the process, because I did not understood that I do not need to use process all the time.

I will give it a try.

Is the following understanding correct:

Process for sequential (a must to react on the clock and the edge of the signal)

no process for combinatory circuits (such as ALU designs)

It is obvious you are just getting started, so I understand. I had no one to ask when I learned to use VHDL. I took a week course and the instructor sucked so badly he answered questions wrong. It\'s one thing not to know, but giving out bad info is terrible.

I won\'t say you should not use a process for combinational circuits. A process is of no value for simple assignments to signals. Processes also have variables which are updated immediately, unlike signals which are not updated until the process ends and the simulation proceeds to the next time step which is a delta time step. That\'s a bit complicated and I\'m happy to explain it if you want. Most people consider that signals are updated at the end of the process which is essentially correct.

Concurrent code does not use variables. Every concurrent assignment is actually a process. It runs whenever any of the inputs change state, just like a process. Essentially all concurrent code produces logic that runs in parallel. Even the process statement is concurrent code creating a process that runs in parallel with other processes including the concurrent logic. Hence the name concurrent.

Variables can used in sequential code such as processes, functions and procedures. They allow code to be written in a similar manner to code written for CPUs which are executed sequentially. For example you can write

a := b + c;
a := a + d;

This would add b, c and d and assign it to a in the order shown. If a were a signal, the last assignment in the process would be the only one taking effect. Notice a different assignment operator is used for signals <= and variables :=

Often beginners confuse processes with subroutines like sequential programming languages use. You don\'t seem to have that confusion.

So there are many ways to do the job. It also makes a difference if you are working with VHDL 2008 or an older version. There are many improvements in 2008 that makes coding easier. Often you must enable VHDL 2008 in your tool even if it is capable.

I hope this helps.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

Thank you so much Rick, that really helps and is highly appreciated.

I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless.

I came from nand2tetris, which has a much more simplified HDL to get the principles of chip design transported/tought. I now wanted to get into a real HDL to implement this chip (a very simple 16bit processor) into an FPGA.

So i learned some of the tutorials from https://vhdlwhiz.com/, which helped alot - for instance all the basic gates and muxers and stuff I could implement easily. But at that point I struggled because of simply not really understanding what a process does and why something within a process is not the same as a simple concurrent logic without any process.

You helped me on that alot and it is now much clearer. I am pretty sure I will stumble accross it again in the future, as things are getting more complicated, but for now.

THANKS A MILLION, really appreciated.
No problem. I didn\'t realize you were working on an actual design. I thought this was a learning exercise.

If you are targeting FPGAs, there is no point in trying to implement a carry lookahead, at least not for 16 bits. Every FPGA I know of uses a fast carry chain optimized in the silicon which runs much faster than any sort of speedup implemented in the LUTs in the FPGA fabric. They use a similar sort of carry speedup involving a transmission gate which is faster than a logic gate. So each stage has a logic delay which all bits execute in parallel and the ripple carry which is a small fraction of a ns per bit.

So unless you are doing the carry lookahead as an exercise, just typing the addition of your signals is all you need to do. Oh, and using ieee.numeric_std. That will let you use signed or unsigned data types for your adder. Or you can use integer types with the range restricted to 16 bits. That could be lesson 2 if you are interested.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
 
R

Rick C

Guest
On Friday, May 15, 2020 at 7:06:42 AM UTC-4, Christoph Linden wrote:
Am Freitag, 15. Mai 2020 09:02:59 UTC+2 schrieb Rick C:
On Friday, May 15, 2020 at 2:00:27 AM UTC-4, Christoph Linden wrote:
Am Freitag, 15. Mai 2020 00:46:01 UTC+2 schrieb Rick C:
Thank you Rick, very helpful.

1. Unfortunately I do not know anymore what the questions should have been. I believe it was in the ballpark how I can do this similar to a structural design but without defining single and gates.

2. The o_sum part. The problem is, that for whatever reason google.groups interpreted part of the code as \"quote\". So if you click on the quote you see, that it is actually two entities. One entity is calculating the carry look ahead and the other is doing the actual add of the four bits.

That is why it looks so weird if you do not unfold the quote.

But anyhow I understood what you was saying and yes, I just used the process, because I did not understood that I do not need to use process all the time.

I will give it a try.

Is the following understanding correct:

Process for sequential (a must to react on the clock and the edge of the signal)

no process for combinatory circuits (such as ALU designs)

It is obvious you are just getting started, so I understand. I had no one to ask when I learned to use VHDL. I took a week course and the instructor sucked so badly he answered questions wrong. It\'s one thing not to know, but giving out bad info is terrible.

I won\'t say you should not use a process for combinational circuits. A process is of no value for simple assignments to signals. Processes also have variables which are updated immediately, unlike signals which are not updated until the process ends and the simulation proceeds to the next time step which is a delta time step. That\'s a bit complicated and I\'m happy to explain it if you want. Most people consider that signals are updated at the end of the process which is essentially correct.

Concurrent code does not use variables. Every concurrent assignment is actually a process. It runs whenever any of the inputs change state, just like a process. Essentially all concurrent code produces logic that runs in parallel. Even the process statement is concurrent code creating a process that runs in parallel with other processes including the concurrent logic. Hence the name concurrent.

Variables can used in sequential code such as processes, functions and procedures. They allow code to be written in a similar manner to code written for CPUs which are executed sequentially. For example you can write

a := b + c;
a := a + d;

This would add b, c and d and assign it to a in the order shown. If a were a signal, the last assignment in the process would be the only one taking effect. Notice a different assignment operator is used for signals <= and variables :=

Often beginners confuse processes with subroutines like sequential programming languages use. You don\'t seem to have that confusion.

So there are many ways to do the job. It also makes a difference if you are working with VHDL 2008 or an older version. There are many improvements in 2008 that makes coding easier. Often you must enable VHDL 2008 in your tool even if it is capable.

I hope this helps.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

Thank you so much Rick, that really helps and is highly appreciated.

I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless.

I came from nand2tetris, which has a much more simplified HDL to get the principles of chip design transported/tought. I now wanted to get into a real HDL to implement this chip (a very simple 16bit processor) into an FPGA.

So i learned some of the tutorials from https://vhdlwhiz.com/, which helped alot - for instance all the basic gates and muxers and stuff I could implement easily. But at that point I struggled because of simply not really understanding what a process does and why something within a process is not the same as a simple concurrent logic without any process.

You helped me on that alot and it is now much clearer. I am pretty sure I will stumble accross it again in the future, as things are getting more complicated, but for now.

THANKS A MILLION, really appreciated.
No problem. I didn\'t realize you were working on an actual design. I thought this was a learning exercise.

If you are targeting FPGAs, there is no point in trying to implement a carry lookahead, at least not for 16 bits. Every FPGA I know of uses a fast carry chain optimized in the silicon which runs much faster than any sort of speedup implemented in the LUTs in the FPGA fabric. They use a similar sort of carry speedup involving a transmission gate which is faster than a logic gate. So each stage has a logic delay which all bits execute in parallel and the ripple carry which is a small fraction of a ns per bit.

So unless you are doing the carry lookahead as an exercise, just typing the addition of your signals is all you need to do. Oh, and using ieee.numeric_std. That will let you use signed or unsigned data types for your adder. Or you can use integer types with the range restricted to 16 bits. That could be lesson 2 if you are interested.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
 
R

Rick C

Guest
On Friday, May 15, 2020 at 7:06:42 AM UTC-4, Christoph Linden wrote:
Am Freitag, 15. Mai 2020 09:02:59 UTC+2 schrieb Rick C:
On Friday, May 15, 2020 at 2:00:27 AM UTC-4, Christoph Linden wrote:
Am Freitag, 15. Mai 2020 00:46:01 UTC+2 schrieb Rick C:
Thank you Rick, very helpful.

1. Unfortunately I do not know anymore what the questions should have been. I believe it was in the ballpark how I can do this similar to a structural design but without defining single and gates.

2. The o_sum part. The problem is, that for whatever reason google.groups interpreted part of the code as \"quote\". So if you click on the quote you see, that it is actually two entities. One entity is calculating the carry look ahead and the other is doing the actual add of the four bits.

That is why it looks so weird if you do not unfold the quote.

But anyhow I understood what you was saying and yes, I just used the process, because I did not understood that I do not need to use process all the time.

I will give it a try.

Is the following understanding correct:

Process for sequential (a must to react on the clock and the edge of the signal)

no process for combinatory circuits (such as ALU designs)

It is obvious you are just getting started, so I understand. I had no one to ask when I learned to use VHDL. I took a week course and the instructor sucked so badly he answered questions wrong. It\'s one thing not to know, but giving out bad info is terrible.

I won\'t say you should not use a process for combinational circuits. A process is of no value for simple assignments to signals. Processes also have variables which are updated immediately, unlike signals which are not updated until the process ends and the simulation proceeds to the next time step which is a delta time step. That\'s a bit complicated and I\'m happy to explain it if you want. Most people consider that signals are updated at the end of the process which is essentially correct.

Concurrent code does not use variables. Every concurrent assignment is actually a process. It runs whenever any of the inputs change state, just like a process. Essentially all concurrent code produces logic that runs in parallel. Even the process statement is concurrent code creating a process that runs in parallel with other processes including the concurrent logic. Hence the name concurrent.

Variables can used in sequential code such as processes, functions and procedures. They allow code to be written in a similar manner to code written for CPUs which are executed sequentially. For example you can write

a := b + c;
a := a + d;

This would add b, c and d and assign it to a in the order shown. If a were a signal, the last assignment in the process would be the only one taking effect. Notice a different assignment operator is used for signals <= and variables :=

Often beginners confuse processes with subroutines like sequential programming languages use. You don\'t seem to have that confusion.

So there are many ways to do the job. It also makes a difference if you are working with VHDL 2008 or an older version. There are many improvements in 2008 that makes coding easier. Often you must enable VHDL 2008 in your tool even if it is capable.

I hope this helps.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

Thank you so much Rick, that really helps and is highly appreciated.

I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless.

I came from nand2tetris, which has a much more simplified HDL to get the principles of chip design transported/tought. I now wanted to get into a real HDL to implement this chip (a very simple 16bit processor) into an FPGA.

So i learned some of the tutorials from https://vhdlwhiz.com/, which helped alot - for instance all the basic gates and muxers and stuff I could implement easily. But at that point I struggled because of simply not really understanding what a process does and why something within a process is not the same as a simple concurrent logic without any process.

You helped me on that alot and it is now much clearer. I am pretty sure I will stumble accross it again in the future, as things are getting more complicated, but for now.

THANKS A MILLION, really appreciated.
No problem. I didn\'t realize you were working on an actual design. I thought this was a learning exercise.

If you are targeting FPGAs, there is no point in trying to implement a carry lookahead, at least not for 16 bits. Every FPGA I know of uses a fast carry chain optimized in the silicon which runs much faster than any sort of speedup implemented in the LUTs in the FPGA fabric. They use a similar sort of carry speedup involving a transmission gate which is faster than a logic gate. So each stage has a logic delay which all bits execute in parallel and the ripple carry which is a small fraction of a ns per bit.

So unless you are doing the carry lookahead as an exercise, just typing the addition of your signals is all you need to do. Oh, and using ieee.numeric_std. That will let you use signed or unsigned data types for your adder. Or you can use integer types with the range restricted to 16 bits. That could be lesson 2 if you are interested.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209
 
N

Nicolas Matringe

Guest
On 2020-05-15 13:06, Christoph Linden wrote:

> I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless.

You don\'t have to put each line in a process, just write concurrent
assignments (which are, actually, implicit processes without all the fuss)

Writing

a <= b and c;

outside of a process is strictly equivalent to

process (b, c)
begin
a <= b and c;
end process;

You can therefore write

a <= b and c;
d <= a or e;

and it will give you exactly d <= (b and c) or e;
as long as it\'s NOT in a process.

Nicolas
 
N

Nicolas Matringe

Guest
On 2020-05-15 13:06, Christoph Linden wrote:

> I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless.

You don\'t have to put each line in a process, just write concurrent
assignments (which are, actually, implicit processes without all the fuss)

Writing

a <= b and c;

outside of a process is strictly equivalent to

process (b, c)
begin
a <= b and c;
end process;

You can therefore write

a <= b and c;
d <= a or e;

and it will give you exactly d <= (b and c) or e;
as long as it\'s NOT in a process.

Nicolas
 
N

Nicolas Matringe

Guest
On 2020-05-15 13:06, Christoph Linden wrote:

> I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless.

You don\'t have to put each line in a process, just write concurrent
assignments (which are, actually, implicit processes without all the fuss)

Writing

a <= b and c;

outside of a process is strictly equivalent to

process (b, c)
begin
a <= b and c;
end process;

You can therefore write

a <= b and c;
d <= a or e;

and it will give you exactly d <= (b and c) or e;
as long as it\'s NOT in a process.

Nicolas
 
C

Christoph Linden

Guest
Am Sonntag, 17. Mai 2020 13:43:58 UTC+2 schrieb Nicolas Matringe:
On 2020-05-15 13:06, Christoph Linden wrote:

I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless.

You don\'t have to put each line in a process, just write concurrent
assignments (which are, actually, implicit processes without all the fuss)

Writing

a <= b and c;

outside of a process is strictly equivalent to

process (b, c)
begin
a <= b and c;
end process;

You can therefore write

a <= b and c;
d <= a or e;

and it will give you exactly d <= (b and c) or e;
as long as it\'s NOT in a process.

Nicolas
Thanks for the explanation ... it comes together step by step. and that is why I am doing this as a learning experience based on an already existing design I did within the nand2tetris course with a very simplified HDL.

Actually the HDL has only structural design and also comes with nothing like processes... My journey goes on now with mixed design and then getting into a full behavioural implementation. As Rick mentioned ... obviously I could simply use sum=a+b; and would be fine. But that was to easy :)
 
C

Christoph Linden

Guest
Am Sonntag, 17. Mai 2020 13:43:58 UTC+2 schrieb Nicolas Matringe:
On 2020-05-15 13:06, Christoph Linden wrote:

I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless.

You don\'t have to put each line in a process, just write concurrent
assignments (which are, actually, implicit processes without all the fuss)

Writing

a <= b and c;

outside of a process is strictly equivalent to

process (b, c)
begin
a <= b and c;
end process;

You can therefore write

a <= b and c;
d <= a or e;

and it will give you exactly d <= (b and c) or e;
as long as it\'s NOT in a process.

Nicolas
Thanks for the explanation ... it comes together step by step. and that is why I am doing this as a learning experience based on an already existing design I did within the nand2tetris course with a very simplified HDL.

Actually the HDL has only structural design and also comes with nothing like processes... My journey goes on now with mixed design and then getting into a full behavioural implementation. As Rick mentioned ... obviously I could simply use sum=a+b; and would be fine. But that was to easy :)
 
C

Christoph Linden

Guest
Am Sonntag, 17. Mai 2020 13:43:58 UTC+2 schrieb Nicolas Matringe:
On 2020-05-15 13:06, Christoph Linden wrote:

I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless.

You don\'t have to put each line in a process, just write concurrent
assignments (which are, actually, implicit processes without all the fuss)

Writing

a <= b and c;

outside of a process is strictly equivalent to

process (b, c)
begin
a <= b and c;
end process;

You can therefore write

a <= b and c;
d <= a or e;

and it will give you exactly d <= (b and c) or e;
as long as it\'s NOT in a process.

Nicolas
Thanks for the explanation ... it comes together step by step. and that is why I am doing this as a learning experience based on an already existing design I did within the nand2tetris course with a very simplified HDL.

Actually the HDL has only structural design and also comes with nothing like processes... My journey goes on now with mixed design and then getting into a full behavioural implementation. As Rick mentioned ... obviously I could simply use sum=a+b; and would be fine. But that was to easy :)
 
R

Rick C

Guest
On Monday, May 18, 2020 at 12:48:24 PM UTC-4, Christoph Linden wrote:
Am Sonntag, 17. Mai 2020 13:43:58 UTC+2 schrieb Nicolas Matringe:
On 2020-05-15 13:06, Christoph Linden wrote:

I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless.

You don\'t have to put each line in a process, just write concurrent
assignments (which are, actually, implicit processes without all the fuss)

Writing

a <= b and c;

outside of a process is strictly equivalent to

process (b, c)
begin
a <= b and c;
end process;

You can therefore write

a <= b and c;
d <= a or e;

and it will give you exactly d <= (b and c) or e;
as long as it\'s NOT in a process.

Nicolas

Thanks for the explanation ... it comes together step by step. and that is why I am doing this as a learning experience based on an already existing design I did within the nand2tetris course with a very simplified HDL.

Actually the HDL has only structural design and also comes with nothing like processes... My journey goes on now with mixed design and then getting into a full behavioural implementation. As Rick mentioned ... obviously I could simply use sum=a+b; and would be fine. But that was to easy :)
You might get more applicable experience trying to program something with a state machine. That can let you see the advantages and disadvantages of processes, procedures, functions and just plain old concurrent logic and forget about coding structurally... I mean as a low level technique stringing gates together.

One that is often taught in school is an elevator. You can start with one that goes between two floors. There is one in a building I frequent and oddly enough it has two buttons, 1 and 2 rather than the one button required since you don\'t really have a choice where to go. You just need an \"other floor\" button.

Maybe I\'ll go into the elevator business and specialize in simplified elevator controls. One button takes you to a random floor. You keep pushing it until you get where you want to go.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209
 
R

Rick C

Guest
On Monday, May 18, 2020 at 12:48:24 PM UTC-4, Christoph Linden wrote:
Am Sonntag, 17. Mai 2020 13:43:58 UTC+2 schrieb Nicolas Matringe:
On 2020-05-15 13:06, Christoph Linden wrote:

I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless.

You don\'t have to put each line in a process, just write concurrent
assignments (which are, actually, implicit processes without all the fuss)

Writing

a <= b and c;

outside of a process is strictly equivalent to

process (b, c)
begin
a <= b and c;
end process;

You can therefore write

a <= b and c;
d <= a or e;

and it will give you exactly d <= (b and c) or e;
as long as it\'s NOT in a process.

Nicolas

Thanks for the explanation ... it comes together step by step. and that is why I am doing this as a learning experience based on an already existing design I did within the nand2tetris course with a very simplified HDL.

Actually the HDL has only structural design and also comes with nothing like processes... My journey goes on now with mixed design and then getting into a full behavioural implementation. As Rick mentioned ... obviously I could simply use sum=a+b; and would be fine. But that was to easy :)
You might get more applicable experience trying to program something with a state machine. That can let you see the advantages and disadvantages of processes, procedures, functions and just plain old concurrent logic and forget about coding structurally... I mean as a low level technique stringing gates together.

One that is often taught in school is an elevator. You can start with one that goes between two floors. There is one in a building I frequent and oddly enough it has two buttons, 1 and 2 rather than the one button required since you don\'t really have a choice where to go. You just need an \"other floor\" button.

Maybe I\'ll go into the elevator business and specialize in simplified elevator controls. One button takes you to a random floor. You keep pushing it until you get where you want to go.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209
 
R

Rick C

Guest
On Monday, May 18, 2020 at 12:48:24 PM UTC-4, Christoph Linden wrote:
Am Sonntag, 17. Mai 2020 13:43:58 UTC+2 schrieb Nicolas Matringe:
On 2020-05-15 13:06, Christoph Linden wrote:

I was aware of the parallelity of execution, but actually the process is only update one time... So you are right, what I would need to do would be putting each line in a process, which is pretty much pointless.

You don\'t have to put each line in a process, just write concurrent
assignments (which are, actually, implicit processes without all the fuss)

Writing

a <= b and c;

outside of a process is strictly equivalent to

process (b, c)
begin
a <= b and c;
end process;

You can therefore write

a <= b and c;
d <= a or e;

and it will give you exactly d <= (b and c) or e;
as long as it\'s NOT in a process.

Nicolas

Thanks for the explanation ... it comes together step by step. and that is why I am doing this as a learning experience based on an already existing design I did within the nand2tetris course with a very simplified HDL.

Actually the HDL has only structural design and also comes with nothing like processes... My journey goes on now with mixed design and then getting into a full behavioural implementation. As Rick mentioned ... obviously I could simply use sum=a+b; and would be fine. But that was to easy :)
You might get more applicable experience trying to program something with a state machine. That can let you see the advantages and disadvantages of processes, procedures, functions and just plain old concurrent logic and forget about coding structurally... I mean as a low level technique stringing gates together.

One that is often taught in school is an elevator. You can start with one that goes between two floors. There is one in a building I frequent and oddly enough it has two buttons, 1 and 2 rather than the one button required since you don\'t really have a choice where to go. You just need an \"other floor\" button.

Maybe I\'ll go into the elevator business and specialize in simplified elevator controls. One button takes you to a random floor. You keep pushing it until you get where you want to go.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209
 
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