W
Weng Tianxiang
Guest
On Monday, March 30, 2015 at 2:18:41 AM UTC-7, diog...@gmail.com wrote:
-dio,
Thank you for your good information.
No matter whether or not I get rich through it, I will perfect my invented method to make contribution to science.
I will have another two successive patent applications about the same topics to publish in this group to perfect "the systematic method of coding wave pipelined circuits in HDL" so that it will be used universally in all modern 4-core processors someday, not mention in FPGA.
If someone is tired of reading new inventions, please stay away and you are not forced or flirted to read those "confusing and snotty" inventions.
Weng
Here are some important sections in my patent application:
New concurrent link statement in HDL
[0137] In order to let a synthesizer identify which code is a wave-pipelining ready code and help check the correctness of connections and paired type between a WPC instantiation and a CPC instantiation, three versions of new concurrent link statement are suggested to be introduced into HDL.
[0138] Here is the definition of new concurrent link statement in bold type based on VHDL-2002:
concurrent_statement ::block_statement
| link_statement
| process_statement
| concurrent_procedure_call_statement
| concurrent_assertion_statement
| concurrent_signal_assignment_statement
| component_instantiation_statement
| generate_statement
link_statement ::[ link_label : ] link_name ( wave_pipelining_component_label ,
critical_path_component_label [ , alias_wave_constant_list ] ) ;
link_label ::= label
link_name ::= link1 | link2 | link3
wave_pipelining_component_label ::= label
critical_path_component_label ::=
series_component_label
|input_delay_component_label
|multiple_copy_component_label
series_component_label ::= label
input_delay_component_label ::= label
multiple_copy_component_label ::= generate_label , copy_component_label
copy_component_label ::= label
label ::= identifier
[0139] The set of following rules is called link statement mechanism:
* Link1 statement links a WPC series_module instantiation with a series CPC instantiation and optional alias wave constants whose initial value is wave constant series_clock_number and which share the wave constant value of the linked WPC series_module.
* Link2 statement links a WPC input_delay_module instantiation with a series or a feedback CPC instantiation, and optional alias wave constants whose initial value is either wave constant series_clock_number or input_clock_number and which share the wave constant value of the linked WPC input_delay_module.
* Link3 statement links a WPC multiple_copy_module instantiation with a generate statement, a series or a feedback CPC instantiation, and optional alias wave constants whose initial value is either wave constant series_clock_number or multiple_copy_number and which share the wave constant value of the linked WPC multiple_copy_module.
* Wave_pipelining_component_label is the label marking the instantiation of a WPC series_module, input_delay_module or multiple_copy_module.
* Critical_path_component_label is the label marking a CPC instantiation.
o Series_component_label is the label marking the instantiation of a series CPC linked by a link1 statement.
o Input_delay_component_label is the label marking the instantiation of a series or a feedback CPC linked by a link2 statement.
o Multiple_copy_component_label contains two labels, the first one is generate_label marking a generate statement which generates multiple copied CPCs, the second is copy_component_label marking the instantiation of one of multiple copied series or feedback CPCs and linked by a link3 statement.
* Both wave_pipelining_component_label and critical_path_component_label must be located within the concurrent statement area of same architecture based on VHDL-2002, and can be referenced before they are defined in a link statement which is located in the same concurrent statement area.
* An alias wave constant must be visible to the link statement it involves.
* When a WPC multiple_copy_module is instantiated and linked with a generate statement through a link3 statement, the wave constant multiple_copy_number in the multiple_copy_module receives its new initial value through wave constant mechanism under slow mode and target mode, respectively, and the linked generate statement uses the wave constant multiple_copy_number constant value to generate 1 or more CPC under slow mode and target mode, respectively. The range used in the generate statement is fixed and must be from 0 to multiple_copy_number-1 or multiple_copy_number-1 downto 0.
The following several sections will not be published because it is related to synthesizing technology:
How a synthesizer determines wave constant values for a linked pair of a WPC and a CPC.
How a synthesizer gets wave constant values of a WPC under target mode.
How a synthesizer gets an alias wave constant value under target mode.
How a designer generates a successful wave-pipelined design in HDL.
Thank you for your patient reading.
Weng
On Sunday, March 29, 2015 at 5:47:01 PM UTC+13, Daniel Kho wrote:
On Saturday, 28 March 2015 19:16:38 UTC+8, Weng Tianxiang wrote:
Why currently VHDL committee has so many difficulties financially to get industries into its activities? One most important reason is that VHDL is now free to use for all related companies and they don't have to make their contributions.
That's the reason why standard bodies have by-laws that make sure any information submitted or discussed within working groups are not encumbered by patents. If you are trying to discuss your patent idea within a working group, you need to declare that the information has been patented. In which case, the Chair will tell the whole group to not use that information in the standardization process. I think this is how it goes for most standard bodies.
See http://www.eda.org/vasg/docs/Patent_disc_appropriate_topics.pdf Page 4:
* The DASC will only accept patented material
under paragraph (a) of IEEE Patent Policy
Where paragraph (a) is found on PDF Page 2 (Slide #1):
a) A general disclaimer to the effect that the patentee will not enforce
any of its present or future patent(s) whose use would be required to
implement either mandatory or optional potions of the proposed IEEE
standard against any person or entity complying with the standard; or
The VASG P1076 effort falls under these conditions, no one is going to get rich on a standard essential patent required to implement the VHDL standard (nor either Verilog standards also under the auspices of DASC).
Also note Page 3 (slide #2):
Inappropriate Topics for IEEE WG Meetings
* Don't discuss licensing terms or conditions
...
-dio,
Thank you for your good information.
No matter whether or not I get rich through it, I will perfect my invented method to make contribution to science.
I will have another two successive patent applications about the same topics to publish in this group to perfect "the systematic method of coding wave pipelined circuits in HDL" so that it will be used universally in all modern 4-core processors someday, not mention in FPGA.
If someone is tired of reading new inventions, please stay away and you are not forced or flirted to read those "confusing and snotty" inventions.
Weng
Here are some important sections in my patent application:
New concurrent link statement in HDL
[0137] In order to let a synthesizer identify which code is a wave-pipelining ready code and help check the correctness of connections and paired type between a WPC instantiation and a CPC instantiation, three versions of new concurrent link statement are suggested to be introduced into HDL.
[0138] Here is the definition of new concurrent link statement in bold type based on VHDL-2002:
concurrent_statement ::block_statement
| link_statement
| process_statement
| concurrent_procedure_call_statement
| concurrent_assertion_statement
| concurrent_signal_assignment_statement
| component_instantiation_statement
| generate_statement
link_statement ::[ link_label : ] link_name ( wave_pipelining_component_label ,
critical_path_component_label [ , alias_wave_constant_list ] ) ;
link_label ::= label
link_name ::= link1 | link2 | link3
wave_pipelining_component_label ::= label
critical_path_component_label ::=
series_component_label
|input_delay_component_label
|multiple_copy_component_label
series_component_label ::= label
input_delay_component_label ::= label
multiple_copy_component_label ::= generate_label , copy_component_label
copy_component_label ::= label
label ::= identifier
[0139] The set of following rules is called link statement mechanism:
* Link1 statement links a WPC series_module instantiation with a series CPC instantiation and optional alias wave constants whose initial value is wave constant series_clock_number and which share the wave constant value of the linked WPC series_module.
* Link2 statement links a WPC input_delay_module instantiation with a series or a feedback CPC instantiation, and optional alias wave constants whose initial value is either wave constant series_clock_number or input_clock_number and which share the wave constant value of the linked WPC input_delay_module.
* Link3 statement links a WPC multiple_copy_module instantiation with a generate statement, a series or a feedback CPC instantiation, and optional alias wave constants whose initial value is either wave constant series_clock_number or multiple_copy_number and which share the wave constant value of the linked WPC multiple_copy_module.
* Wave_pipelining_component_label is the label marking the instantiation of a WPC series_module, input_delay_module or multiple_copy_module.
* Critical_path_component_label is the label marking a CPC instantiation.
o Series_component_label is the label marking the instantiation of a series CPC linked by a link1 statement.
o Input_delay_component_label is the label marking the instantiation of a series or a feedback CPC linked by a link2 statement.
o Multiple_copy_component_label contains two labels, the first one is generate_label marking a generate statement which generates multiple copied CPCs, the second is copy_component_label marking the instantiation of one of multiple copied series or feedback CPCs and linked by a link3 statement.
* Both wave_pipelining_component_label and critical_path_component_label must be located within the concurrent statement area of same architecture based on VHDL-2002, and can be referenced before they are defined in a link statement which is located in the same concurrent statement area.
* An alias wave constant must be visible to the link statement it involves.
* When a WPC multiple_copy_module is instantiated and linked with a generate statement through a link3 statement, the wave constant multiple_copy_number in the multiple_copy_module receives its new initial value through wave constant mechanism under slow mode and target mode, respectively, and the linked generate statement uses the wave constant multiple_copy_number constant value to generate 1 or more CPC under slow mode and target mode, respectively. The range used in the generate statement is fixed and must be from 0 to multiple_copy_number-1 or multiple_copy_number-1 downto 0.
The following several sections will not be published because it is related to synthesizing technology:
How a synthesizer determines wave constant values for a linked pair of a WPC and a CPC.
How a synthesizer gets wave constant values of a WPC under target mode.
How a synthesizer gets an alias wave constant value under target mode.
How a designer generates a successful wave-pipelined design in HDL.
Thank you for your patient reading.
Weng