max operation frequency of a gate

Guest
hi all ,

if the prop delay of a gate is say 4 ns , then what is the max
frequency that can be applied to the input ...is it 1/Tpd...or is
greater

THanks
Manan
 
manan.kathuria@gmail.com wrote:
hi all ,

if the prop delay of a gate is say 4 ns , then what is the max
frequency that can be applied to the input ...is it 1/Tpd...or is
greater

THanks
Manan
Click to expand...
You should also consider the impact of rise and fall times on waveform
shape.
 
Andrew Holme wrote...
manan.kathuria@gmail.com wrote:

if the prop delay of a gate is say 4 ns , then what is the max
frequency that can be applied to the input ...is it 1/Tpd...
or is greater
Click to expand...
Well, 1 / 2*Tpd would be closer.

You should also consider the impact of rise and fall times on
waveform shape.
Click to expand...
I agree, and this depends dramatically on the circuitry within
the gate. But in general, even for unloaded outputs, I'd say the
maximum frequency is below that predicted from the formulas above.


--
Thanks,
- Win
 
Im not so much concerned about the shape of the waveform ...what im
trying to figure out is whether the input sampling window for a gate is
the same as the rise/fall time ..or is it lesser?
 
if the prop delay of a gate is say 4 ns , then what is the max
frequency that can be applied to the input ...is it 1/Tpd...or is
greater
Click to expand...
You can apply any frequency you want to the input- just be sure you do
not exceed the min/max voltage levels.
 
mann! wrote...
Im not so much concerned about the shape of the waveform ... what
im trying to figure out is whether the input sampling window for
a gate is the same as the rise/fall time ..or is it lesser?
Click to expand...
Gates don't sample, but flip flops do. They have a very small
sample time indeed, compared to the propagation delay.


--
Thanks,
- Win
 
The positive delay can be different than the negative delay. Therefore, the
max freq is 1/(Tpdp +Tpdn). This also assumes that the input is a square
wave and not a ramp which it probably is.

Harold
<manan.kathuria@gmail.com> wrote in message
news:1109493878.730157.277800@f14g2000cwb.googlegroups.com...
hi all ,

if the prop delay of a gate is say 4 ns , then what is the max
frequency that can be applied to the input ...is it 1/Tpd...or is
greater

THanks
Manan
Click to expand...
 
On Sun, 27 Feb 2005 00:44:38 -0800, manan.kathuria wrote:

hi all ,

if the prop delay of a gate is say 4 ns , then what is the max
frequency that can be applied to the input ...is it 1/Tpd...or is
greater
Click to expand...
The smart-aleck answer, of course, is that there is no limit to
the frequency that can be applied at the input. The operative
parameter, I'd think, would be the maximum frequency where it
reliably functions.

And actually, prop. delay doesn't say how fast the chip can
switch from high to low (or l->h) - only how long it takes for
that transistion to get from input to output.

Isn't it in the data sheet?

Thanks,
Rich
 
I read in sci.electronics.design that Rich Grise <richgrise@example.net>
wrote (in <pan.2005.02.27.19.52.08.626349@example.net>) about 'max
operation frequency of a gate', on Sun, 27 Feb 2005:

The smart-aleck answer, of course, is that there is no limit to the
frequency that can be applied at the input. The operative parameter, I'd
think, would be the maximum frequency where it reliably functions.
Click to expand...
Yes, even I refrained from pointing out that you could shine a blue
laser on the input pin. I decided that the OP didn't even know what
question to ask, so I left it to others to enlighten, if possible.
--
Regards, John Woodgate, OOO - Own Opinions Only.
The good news is that nothing is compulsory.
The bad news is that everything is prohibited.
http://www.jmwa.demon.co.uk Also see http://www.isce.org.uk
 
manan.kathuria@gmail.com wrote:

hi all ,

if the prop delay of a gate is say 4 ns , then what is the max
frequency that can be applied to the input ...is it 1/Tpd...or is
greater
Click to expand...
The data sheet generally gives the answer ( for reliable operation ).
Clock gates too fast continually and you're likely to overheat them (
like overclocking cpus ).


Graham
 
why is it that a flip flop has a sample time , but a gate doesnt???

Is it coz of the feedback used in a flip flop?
 
On 2 Mar 2005 03:07:59 -0800, "mann!" <manan.kathuria@gmail.com>
wrote:

why is it that a flip flop has a sample time , but a gate doesnt???

Is it coz of the feedback used in a flip flop?
Click to expand...
An edge-triggered flip-flop (like a 74LS74) will "read" the state of
the D input _at the time of the positive clock transition_ - that is
the "sample time".

A simple logic gate just passes the state of its inputs through to its
output (doing whatever logic is required along the way). It does not
"sample" the inputs at discrete times - it continuously examines them.




--
Peter Bennett VE7CEI
email: peterbb4 (at) interchange.ubc.ca
GPS and NMEA info and programs: http://vancouver-webpages.com/peter/index.html
Newsgroup new user info: http://vancouver-webpages.com/nnq
 
Peter Bennett wrote:

An edge-triggered flip-flop (like a 74LS74) will "read" the state of
the D input _at the time of the positive clock transition_ - that is
the "sample time".

A simple logic gate just passes the state of its inputs through to its
output (doing whatever logic is required along the way). It does not
"sample" the inputs at discrete times - it continuously examines them.
Click to expand...
Not quite true- a FF will read the state of the gate which conforms to
its setup and hold times. It's worth noting that one or both of these
can be negative- i.e. the time the state is actually 'read' could be
slightly before or after the clock edge.

It's also worth noting that inputs that DON'T conform can produce odd
effects, like a transient pulse at the output- I remember falling over
this in one of my first designs, had to change to a 74S74 instead of LS!

Similarly, with logic gates, if it's not Schmitty, you can't say what
the output will be if the Tr, Tf and state time are less than the
propogation delay.
 
Jim Thompson wrote:
On Wed, 02 Mar 2005 10:14:41 -0800, Peter Bennett
peterbb@nowhere.invalid> wrote:

A simple logic gate just passes the state of its inputs through to its
output (doing whatever logic is required along the way). It does not
"sample" the inputs at discrete times - it continuously examines them.


"Continuously", AKA Analog ;-)

...Jim Thompson
Click to expand...
But electronics relies on the movement of discrete (countable) charge
units (electrons), AKA digital ;-))
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com
 
On Sat, 05 Mar 2005 21:03:38 GMT, Tim Hubberstey <bogus@bogusname.com>
wrote:

Jim Thompson wrote:
On Wed, 02 Mar 2005 10:14:41 -0800, Peter Bennett
peterbb@nowhere.invalid> wrote:

A simple logic gate just passes the state of its inputs through to its
output (doing whatever logic is required along the way). It does not
"sample" the inputs at discrete times - it continuously examines them.


"Continuously", AKA Analog ;-)

...Jim Thompson

But electronics relies on the movement of discrete (countable) charge
units (electrons), AKA digital ;-))
Click to expand...
Sure. At the noise floor level :)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.
 
On Sat, 05 Mar 2005 16:22:03 -0700, Jim Thompson
<thegreatone@example.com> wrote:

On Sat, 05 Mar 2005 21:03:38 GMT, Tim Hubberstey <bogus@bogusname.com
wrote:

Jim Thompson wrote:
On Wed, 02 Mar 2005 10:14:41 -0800, Peter Bennett
peterbb@nowhere.invalid> wrote:

A simple logic gate just passes the state of its inputs through to its
output (doing whatever logic is required along the way). It does not
"sample" the inputs at discrete times - it continuously examines them.


"Continuously", AKA Analog ;-)

...Jim Thompson

But electronics relies on the movement of discrete (countable) charge
units (electrons), AKA digital ;-))

Sure. At the noise floor level :)
Click to expand...
---
So, you're admitting that since charge is ultimately quantifiable, and
discrete, "analog" quantities are granular?

--
John Fields
 
On Sat, 05 Mar 2005 18:31:41 -0600, John Fields wrote:

On Sat, 05 Mar 2005 16:22:03 -0700, Jim Thompson
thegreatone@example.com> wrote:

On Sat, 05 Mar 2005 21:03:38 GMT, Tim Hubberstey <bogus@bogusname.com
wrote:

Jim Thompson wrote:
On Wed, 02 Mar 2005 10:14:41 -0800, Peter Bennett
peterbb@nowhere.invalid> wrote:

A simple logic gate just passes the state of its inputs through to its
output (doing whatever logic is required along the way). It does not
"sample" the inputs at discrete times - it continuously examines them.


"Continuously", AKA Analog ;-)

...Jim Thompson

But electronics relies on the movement of discrete (countable) charge
units (electrons), AKA digital ;-))

Sure. At the noise floor level :)

---
So, you're admitting that since charge is ultimately quantifiable, and
discrete, "analog" quantities are granular?
Click to expand...
At some point isn't *everything*?

--
Keith
 
On Sun, 06 Mar 2005 00:09:59 -0500, the renowned keith
<krw@att.bizzzz> wrote:

On Sat, 05 Mar 2005 18:31:41 -0600, John Fields wrote:

On Sat, 05 Mar 2005 16:22:03 -0700, Jim Thompson
thegreatone@example.com> wrote:

On Sat, 05 Mar 2005 21:03:38 GMT, Tim Hubberstey <bogus@bogusname.com
wrote:

Jim Thompson wrote:
On Wed, 02 Mar 2005 10:14:41 -0800, Peter Bennett
peterbb@nowhere.invalid> wrote:

A simple logic gate just passes the state of its inputs through to its
output (doing whatever logic is required along the way). It does not
"sample" the inputs at discrete times - it continuously examines them.


"Continuously", AKA Analog ;-)

...Jim Thompson

But electronics relies on the movement of discrete (countable) charge
units (electrons), AKA digital ;-))

Sure. At the noise floor level :)

---
So, you're admitting that since charge is ultimately quantifiable, and
discrete, "analog" quantities are granular?

At some point isn't *everything*?
Click to expand...
Is time granular?


Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
 
On Sun, 06 Mar 2005 02:12:30 -0500, Spehro Pefhany
<speffSNIP@interlogDOTyou.knowwhat> wrote:

On Sun, 06 Mar 2005 00:09:59 -0500, the renowned keith
krw@att.bizzzz> wrote:

On Sat, 05 Mar 2005 18:31:41 -0600, John Fields wrote:

On Sat, 05 Mar 2005 16:22:03 -0700, Jim Thompson
thegreatone@example.com> wrote:

On Sat, 05 Mar 2005 21:03:38 GMT, Tim Hubberstey <bogus@bogusname.com
wrote:

Jim Thompson wrote:
On Wed, 02 Mar 2005 10:14:41 -0800, Peter Bennett
peterbb@nowhere.invalid> wrote:

A simple logic gate just passes the state of its inputs through to its
output (doing whatever logic is required along the way). It does not
"sample" the inputs at discrete times - it continuously examines them.


"Continuously", AKA Analog ;-)

...Jim Thompson

But electronics relies on the movement of discrete (countable) charge
units (electrons), AKA digital ;-))

Sure. At the noise floor level :)

---
So, you're admitting that since charge is ultimately quantifiable, and
discrete, "analog" quantities are granular?

At some point isn't *everything*?

Is time granular?
Click to expand...
1e-44 seconds, roughly.

John
 
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