Make program stop

[AL]

Hi everyone, My program is supposed to loop and loop until an error occur, then it supposed to stop. Is there a way to do this in Verilog and Spartan3? I want to be able to get a message pop up on the PC when this error occurs also. Is it possible to do this with JTAG? Or is there another way? Thanks, Ann

 

[glen herrmannsfeldt]

AL wrote:

Hi everyone, My program is supposed to loop and loop until an error occur,
then it supposed to stop. Is there a way to do this in Verilog and Spartan3?

I want to be able to get a message pop up on the PC when this
error occurs also.
Is it possible to do this with JTAG? Or is there another way?

Verilog describes logic, and it is possible to make logic to do
that. You can use a counter, for example.

AL also wrote:

I want it to sample these data coming in and then store the
data to different bins, i.e. there are data somewhere from 0
to 255 going into the FPGA, the FPGA reads this data and
increase the bin count, for example, the FPGA sees 3 coming
in, so bin3 count= 1, then a 10 comes in, bin10 count = 1,
then 3 comes in, so bin3 count = 2, etc....

This is the property of RAM, which is easy to write in verilog,
it looks pretty much like a C array. Don't forget to clear it
before writing to it. To increase the count you will need to
read it, increment it, and write it, most likely in separate
clock cycles (clock edges if you are really lucky).

Good luck!

-- glen

 

[Ann]

Hi, I didn't mean stop completely but just stop what it's doing, but now that I think about it, I guess I can just make it output some kind of default value or something. But what about get it to pop up a message "DONE" or "ERROR" or something so that the user can see? Thanks, Ann

 

[Alun Harford]

"Ann" <ann.lai@analog.com> wrote in message news:ee8bf07.3@webx.sUN8CHnE...

Hi, I didn't mean stop completely but just stop what it's doing, but now
that I think about it, I guess I can just make it output some kind of

default value or something. But what about get it to pop up a message "DONE"
or "ERROR" or something so that the user can see? Thanks, Ann

On what?
It's an FPGA - it has wires going in and wires coming out. If you've turned
it into something fancy that can output to a screen (or printer, serial port
or whatever) then the answer depends on how you did that.
If you're running a verilog simulator, there will probably be calls you can
make - but I don't think I've ever used them so I can't remember what they
are (I'm sure I'll regret that when it gets asked in my exams, but there we
go)

Alun Harford

 

[jtw]

I googled "verilog stop" and quickly came back with $stop. (Note: I
haven't used verilog [much] in about 8 years. Been using the other major
HDL.) E.g.,
http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html

I don't know if verilog has a direct equivalent to VHDL's "report" and
"assert" commands, but I'm sure you could work something out with one of the
following (from that link):

$display("text_with_format_specifiers", signal, signal, ... );

Prints the formatted message once when the statement is executed during
simulation. A newline is automatically added to the text printed.

$write("text_with_format_specifiers", signal, signal, ... );

Like $display statement, except that no newline is added.

$strobe("text_with_format_specifiers", signal, signal, ... );

Like the $display statement, except that the printing of the text is delayed
until all simulation events in the current time step have executed.

Jason

"AL" <ann.lai@analog.com> wrote in message news:ee8bf07.1@webx.sUN8CHnE...

Thanks glen for the response, but what about making the program stop
completely and pop up a message that says something like "ERROR", is there
a way to implement that? I have tried using "disable" but that won't
compile, I think it was unsupported or something. Thanks, Ann