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Hello there!
Does anybody have tried to optimize power in cadence PKS with sleep_mode?
I do get nice results using clock gating but sleep_mode makes the area
of the design to substantially increase and brings no power saving at
all. I suppose that the sleep-mode logic should be committed only when
timing is not a issue and power is saved.
I tried in two blocks, with no success, one is supposed to
have lots of arithmetic operations (video scaling). I tried different
flows even the one where I stop for power simulation and generate a
toggle count file from the gate level simulation of the netlist.
Anybody with experience on that? It can't be that the tool generates
the additional logic if no power saving comes along with it.
Best Regards
Does anybody have tried to optimize power in cadence PKS with sleep_mode?
I do get nice results using clock gating but sleep_mode makes the area
of the design to substantially increase and brings no power saving at
all. I suppose that the sleep-mode logic should be committed only when
timing is not a issue and power is saved.
I tried in two blocks, with no success, one is supposed to
have lots of arithmetic operations (video scaling). I tried different
flows even the one where I stop for power simulation and generate a
toggle count file from the gate level simulation of the netlist.
Anybody with experience on that? It can't be that the tool generates
the additional logic if no power saving comes along with it.
Best Regards