library xul;

[Michael Nicklas]

Hi

I am currently trying to replicate a core provided by a manufacturer which
was developed on older Xilinx tools.

In a dual port ram module generated using an early version of COREGen a
library called 'xul' is referenced.

I have conducted searches on the groups and have only found posts dating
from around 1999/2000.

Another library it has difficulties locating is the std.textio packages.

Does this sound like an overall larger problem with accessing libraries or
does it merely stem from the older tools.

I am using ISE 5.1i

here is the header for the file:

-- output of CoreGen module generator
-- $Header: dpbmemVHT.vhd,v 1.5 1998/06/29 23:29:18 hare Exp $
-- ************************************************************************
-- Copyright 1997 - Xilinx, Inc.
-- All rights reserved.
-- ************************************************************************
--
-- Description:
-- Parameterized Dual Port RAM
--

library std;
use std.textio.all;
--
library ieee;
use ieee.std_logic_1164.all;
--
library xul;
use xul.ul_utils.all;
--
ENTITY rm32x512 IS
....
....
....
etc.




Any suggestions would be greatly appreciated.

Thanks in advance.

--
Cheers!

Mike

 

[Alan Fitch]

In a dual port ram module generated using an early version of
COREGen a
library called 'xul' is referenced.

Have a look at answer record 8281 on www.xilinx.com, this explains

the xul library and that it existed in coregen pre xilinx 2.1i.

Another library it has difficulties locating is the std.textio
packages.

This is a standard VHDL library, and will be available in any
VHDL simulator in the STD library. It's not synthesisable
as it's used for text input/output.

regards

Alan


--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

The contents of this message may contain personal views which are not
the
views of Doulos Ltd., unless specifically stated.

 

[Alan Fitch]

Another library it has difficulties locating is the std.textio
packages.


This is a standard VHDL library, and will be available in any
^^^^^^^

sorry, package


Alan



--
Alan Fitch
Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com

 

[Amontec Team]

Hi,

Re-write a second architecture of the rm32x512, and map the entity to
your arch.

We can help you for this task if you need (! not for free). We do that
before.
contact laurent.gauch@amontec.com

Michael Nicklas wrote:

Hi

I am currently trying to replicate a core provided by a manufacturer which
was developed on older Xilinx tools.

In a dual port ram module generated using an early version of COREGen a
library called 'xul' is referenced.

I have conducted searches on the groups and have only found posts dating
from around 1999/2000.

Another library it has difficulties locating is the std.textio packages.

Does this sound like an overall larger problem with accessing libraries or
does it merely stem from the older tools.

I am using ISE 5.1i

here is the header for the file:

-- output of CoreGen module generator
-- $Header: dpbmemVHT.vhd,v 1.5 1998/06/29 23:29:18 hare Exp $
-- ************************************************************************
-- Copyright 1997 - Xilinx, Inc.
-- All rights reserved.
-- ************************************************************************
--
-- Description:
-- Parameterized Dual Port RAM
--

library std;
use std.textio.all;
--
library ieee;
use ieee.std_logic_1164.all;
--
library xul;
use xul.ul_utils.all;
--
ENTITY rm32x512 IS
...
...
...
etc.




Any suggestions would be greatly appreciated.

Thanks in advance.

--
Cheers!

Mike