M
Michael Nicklas
Guest
Hi
I am currently trying to replicate a core provided by a manufacturer which
was developed on older Xilinx tools.
In a dual port ram module generated using an early version of COREGen a
library called 'xul' is referenced.
I have conducted searches on the groups and have only found posts dating
from around 1999/2000.
Another library it has difficulties locating is the std.textio packages.
Does this sound like an overall larger problem with accessing libraries or
does it merely stem from the older tools.
I am using ISE 5.1i
here is the header for the file:
-- output of CoreGen module generator
-- $Header: dpbmemVHT.vhd,v 1.5 1998/06/29 23:29:18 hare Exp $
-- ************************************************************************
-- Copyright 1997 - Xilinx, Inc.
-- All rights reserved.
-- ************************************************************************
--
-- Description:
-- Parameterized Dual Port RAM
--
library std;
use std.textio.all;
--
library ieee;
use ieee.std_logic_1164.all;
--
library xul;
use xul.ul_utils.all;
--
ENTITY rm32x512 IS
....
....
....
etc.
Any suggestions would be greatly appreciated.
Thanks in advance.
--
Cheers!
Mike
I am currently trying to replicate a core provided by a manufacturer which
was developed on older Xilinx tools.
In a dual port ram module generated using an early version of COREGen a
library called 'xul' is referenced.
I have conducted searches on the groups and have only found posts dating
from around 1999/2000.
Another library it has difficulties locating is the std.textio packages.
Does this sound like an overall larger problem with accessing libraries or
does it merely stem from the older tools.
I am using ISE 5.1i
here is the header for the file:
-- output of CoreGen module generator
-- $Header: dpbmemVHT.vhd,v 1.5 1998/06/29 23:29:18 hare Exp $
-- ************************************************************************
-- Copyright 1997 - Xilinx, Inc.
-- All rights reserved.
-- ************************************************************************
--
-- Description:
-- Parameterized Dual Port RAM
--
library std;
use std.textio.all;
--
library ieee;
use ieee.std_logic_1164.all;
--
library xul;
use xul.ul_utils.all;
--
ENTITY rm32x512 IS
....
....
....
etc.
Any suggestions would be greatly appreciated.
Thanks in advance.
--
Cheers!
Mike