ISE 6.1 with synplify : pin assignments

[Dave]

Hi,
I'm using ise 6.1 to write, synthesise and implement my designs. I'm now
trying to use synplify to synthesize without leaving the ise gui. Everything
works fine, except that xilinx doesn't seem to pass the .ucf file with my
pin assignments to synplify. The resulting .edf file doesn't have any
constraints associatted with it, and ise cannot use the .ucf with the .edf.
Is it possible to still use the xilinx constraints editor to generate the
..ucf, or I absolutely need to open synplify and recreate all my constraints
in their scope editor?

Rgds,
David

 

[Erez Birenzwig]

Synplify uses an SDC file to define the pin location, type, timing
constrains etc.
After synthesis it generate a UCF file for the EDIF file it generated and
this can be used with Xilinx tools.

You should probably read the documentation for Synplify synthesis flow.

Regards,
Erez.
"Dave" <gretzteam@hotmail.com> wrote in message
news:8uGdnTEajNgemSWiRVn-jg@comcast.com...

Hi,
I'm using ise 6.1 to write, synthesise and implement my designs. I'm now
trying to use synplify to synthesize without leaving the ise gui.
Everything
works fine, except that xilinx doesn't seem to pass the .ucf file with my
pin assignments to synplify. The resulting .edf file doesn't have any
constraints associatted with it, and ise cannot use the .ucf with the
..edf.
Is it possible to still use the xilinx constraints editor to generate the
.ucf, or I absolutely need to open synplify and recreate all my
constraints
in their scope editor?

Rgds,
David