Is it a bug of synplify?

K

Kot

Guest
I'm using Synplify for Actel ProASIC.
I was writing a portion of design where I just have to
put some registers that acts like some memory to CPU.
It did not work and after simplifying some section of code
to see if the synthesis tool is doing what it is supposed to do,
I found this -- look at the codes in "mypak".
when the constants are defined using plain literal, it synthesize
with no problem. But when the constant values are defined
using function provided by 1164 package then it does not work.
Is it a bug? or I misunderstood VHDL?

-- emailing your knowledge/opinion directly to me is more welcome ;-)

Jihwan
jihwan2@hotmail.com


library ieee;
use ieee.std_logic_1164.all;

package mypak is
subtype addrword is std_logic_vector(3 downto 0);
subtype appword is std_logic;

-- it works this way
--constant aa_reg1 : addrword := "0010";
--constant aa_reg2 : addrword := "0101";
--constant aa_reg3 : addrword := "1010";

-- but not in this way. why?
constant aa_reg1 : addrword := to_x01(x"2");
constant aa_reg2 : addrword := to_x01(x"5");
constant aa_reg3 : addrword := to_x01(x"a");
end package mypak;


library ieee;
use ieee.std_logic_1164.all;
use work.mypak.all;

entity test is
port(
ad : in addrword;
nce : in std_logic;
nwr : in std_logic;
da : inout appword;
q1 : out appword;
q2 : out appword;
q3 : out appword
);
end entity test;

architecture a1 of test is

signal reg1, reg2, reg3 : appword;

begin
q1 <= reg1;
q2 <= reg2;
q3 <= reg3;
process (nce, nwr, ad)
begin
if nce = '0' then
if rising_edge(nwr) then
if ad = aa_reg1 then
reg1 <= da;
elsif ad = aa_reg2 then
reg2 <= da;
elsif ad = aa_reg3 then
reg3 <= da;
end if;
end if;
end if;
end process;
end architecture a1;
 
See comments below


Kot wrote:
I'm using Synplify for Actel ProASIC.
I was writing a portion of design where I just have to
put some registers that acts like some memory to CPU.
It did not work and after simplifying some section of code
to see if the synthesis tool is doing what it is supposed to do,
I found this -- look at the codes in "mypak".
when the constants are defined using plain literal, it synthesize
with no problem. But when the constant values are defined
using function provided by 1164 package then it does not work.
Is it a bug? or I misunderstood VHDL?

-- emailing your knowledge/opinion directly to me is more welcome ;-)

Jihwan
jihwan2@hotmail.com


library ieee;
use ieee.std_logic_1164.all;

package mypak is
subtype addrword is std_logic_vector(3 downto 0);
subtype appword is std_logic;

-- it works this way
--constant aa_reg1 : addrword := "0010";
--constant aa_reg2 : addrword := "0101";
--constant aa_reg3 : addrword := "1010";

-- but not in this way. why?
constant aa_reg1 : addrword := to_x01(x"2");
constant aa_reg2 : addrword := to_x01(x"5");
constant aa_reg3 : addrword := to_x01(x"a");
Click to expand...
Try this:

constant aa_reg1: addrword := X"2";

and so on ..

end package mypak;


library ieee;
use ieee.std_logic_1164.all;
use work.mypak.all;

entity test is
port(
ad : in addrword;
nce : in std_logic;
nwr : in std_logic;
da : inout appword;
q1 : out appword;
q2 : out appword;
q3 : out appword
);
end entity test;

architecture a1 of test is

signal reg1, reg2, reg3 : appword;

begin
q1 <= reg1;
q2 <= reg2;
q3 <= reg3;
Click to expand...

process (nce, nwr, ad)
begin
if nce = '0' then
if rising_edge(nwr) then
if ad = aa_reg1 then
reg1 <= da;
elsif ad = aa_reg2 then
reg2 <= da;
elsif ad = aa_reg3 then
reg3 <= da;
end if;
end if;
end if;
end process;
Click to expand...
You use the nwr as a clock signal this is ok, but what about the nce?
This may cause the problem. Because the tool may not understand what you
want, and I am also not sure. So let's suppose that the nce is the clock
enable signal or chip select:

Try this:

process (nwr)
begin
if rising_edge(nwr) then
if nce = '0' then
if ad = aa_reg1 then
reg1 <= da;
elsif ad = aa_reg2 then
reg2 <= da;
elsif ad = aa_reg3 then
reg3 <= da;
end if;
end if;
end if;
end process;

This will give you registers which are clocked with nwr and nce as
enable signal. There will generate an address decoder and a multiplexer
or priority encoder that selects the signal dependant on the address.


end architecture a1;
Click to expand...
Chris
 
Kot wrote:

when the constants are defined using plain literal, it synthesize
with no problem. But when the constant values are defined
using function provided by 1164 package then it does not work.
Is it a bug? or I misunderstood VHDL?
....
-- but not in this way. why?
constant aa_reg1 : addrword := to_x01(x"2");
Click to expand...
Because to_x01 is defined for multiple vector types.

There is no reason to use to_x01 to
declare a constant, so consider:

constant aa_reg1 : addrword := x"2";

If to_x01 were required, you would have to say:

constant aa_reg1 : addrword := to_x01(addrword'(x"2"));

But you don't.

Consider simulation before synthesis.

-- Mike Treseler
 
Thank you, Mike & Chris.

I've tried 4 different ways.
Here's result if you'd like to know.
I understand that there's no single vendor who
support full definition of VHDL language but
I guess this may be a bug even within the VHDL subset
that Simplify supports.

Jihwan Song

-- mypak
-- T10.vhd
-- going back to T1.vhd

library ieee;
use ieee.std_logic_1164.all;

package mypak is
subtype addrword is std_logic_vector(3 downto 0);
subtype appword is std_logic;

-- it works this way
--constant aa_reg1 : addrword := "0010";
--constant aa_reg2 : addrword := "0101";
--constant aa_reg3 : addrword := "1010";

-- but in this way. why?
--constant aa_reg1 : addrword := to_x01(x"2");
--constant aa_reg2 : addrword := to_x01(x"5");
--constant aa_reg3 : addrword := to_x01(x"a");

-- this works too.
constant aa_reg1 : addrword := X"2";
constant aa_reg2 : addrword := X"5";
constant aa_reg3 : addrword := X"a";

-- look at the decl. section of architecture a1 : another way around
end package mypak;


-- T10.vhd
-- going back to T1.vhd

library ieee;
use ieee.std_logic_1164.all;
use work.mypak.all;

entity test is
port(
ad : in addrword;
nce : in std_logic;
nwr : in std_logic;
da : inout appword;
q1 : out appword;
q2 : out appword;
q3 : out appword
);
end entity test;

architecture a1 of test is

signal reg1, reg2, reg3 : appword;

-- this works too!
--constant aa_reg1 : addrword := to_x01(x"2");
--constant aa_reg2 : addrword := to_x01(x"5");
--constant aa_reg3 : addrword := to_x01(x"a");

begin
q1 <= reg1;
q2 <= reg2;
q3 <= reg3;
process (nce, nwr, ad)
begin
if nce = '0' then
if rising_edge(nwr) then
if ad = aa_reg1 then
reg1 <= da;
elsif ad = aa_reg2 then
reg2 <= da;
elsif ad = aa_reg3 then
reg3 <= da;
end if;
end if;
end if;
end process;
end architecture a1;
 
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