IR2110 gate driver issues.

[Harry Dellamano]

"Winfield Hill" <hill_a@t_rowland-dotties-harvard-dot.s-edu> wrote in
message news:d8c0jn0q74@drn.newsguy.com...

Pooh Bear wrote...

Winfield Hill wrote:

Pooh Bear wrote...

I'm using an IR2110 high and low side gate driver in a smps that
I mentioned some time back in the group under the thread 'should
I use a SG3525'.

I've had some 'odd' power device failures that I didn't expect in
entirely benign situations, such as the half bridge output simply
driving the primary of my transformer.

Cut lots of good stuff.................
It takes an experienced designer to make a reliable switcher.


--
Thanks,
- Win

Ok, EL101, how to design a bullet proof half bridge gate driver.

1. Your IR2110 is ok but you must protect it from: FET Cdg>Cgs causing
large currents into the lower gate driver when the bridge switches high,
large negitive transients at the output (top FET source and bottom FET
drain) when the topside turns off you may get an inductive kick to -20V,
Inductance in the driver gate source loop. This is cured with NPN/PNP
emitter followers drivers and their high side storage capacitors placed at
the gate source leads with a 18V zener placed across them. The IR2110 can
then be safely inches away driving thru a 100 ohm resistor. Zetex has some
great NPN/PNP transistors in small packages that have <100m ohms Ron and
will drive 10 amps <50nS if needed.

2. Even with suitable dead time, if the circuit goes into chaotic operation
and a parasitic diode turns on, the trr can be so long that it will not turn
off soon enough and before the other FET turns on and blows something. Do
not use standard trr FETs. Use FETs with fast diodes <250nS made by most
manufactures now. Digikey has a nice STP11NM50FD. The FD means Fast
parasitic Diodes that will save your butt.

Oh got to go to EL101,

Harry

 

[Winfield Hill]

Harry Dellamano wrote...

... Use FETs with fast diodes <250nS made by most manufactures now.
Digikey has a nice STP11NM50FD. The FD means Fast parasitic Diodes
that will save your butt.

That's the STP11NM60FD, right? Not to be confused with ST's _FP
parts, which are insulated packages. The STP11NM60FPFD is OK. :&gt

Like I was saying, don't let these FET diodes conduct. But if they
must conduct, a fast diode that reduces the current buildup in the
leakage inductance before the current snapoff helps a lot. There
are also soft-recovery-diode types that one can use.


--
Thanks,
- Win

 

[R Adsett]

In article <42A8F5D9.7D571642@hotmail.com>,
rabbitsfriendsandrelations@hotmail.com says...

Terry Given wrote:

Pooh Bear wrote:

what caps are you using for your bootstrap supplies?

Box polyester film. You gonna say I should be using ceramic ?

Add a electrolytic of some sort for long term hold up if the high sides
are going to be on for a while.

I don't see whyhaving the FETs turn off when the power goes low is an
issue though. Hmm, unless they are oscillating on/off at high frequency
as the power is sagging. I didn't think the 2110s were prone to that
but...

Robert

 

[Joerg]

Hello Graham,

Guess what I sketched late this afternoon ! With an LM393. It may be wise
to OR my own UVLO on both supervisory and main bus rails.

Great. Although I tend to turn that extra dime for the comparator around
and around, then usually end up with "poor man's" ORing with transistors.

Regards, Joerg

http://www.analogconsultants.com

 

[Pooh Bear]

Joerg wrote:

Hello Graham,

Guess what I sketched late this afternoon ! With an LM393. It may be wise
to OR my own UVLO on both supervisory and main bus rails.

Great. Although I tend to turn that extra dime for the comparator around
and around, then usually end up with "poor man's" ORing with transistors.

Hah - I used some diode ORing on the separate plug-in pcb that has supervisory
stuff. It works fine !

Graham

 

[Pooh Bear]

Terry Given wrote:

Pooh Bear wrote:

make sure there isnt too much ESR, the capacitance is stable with
voltage & temperature, its happy with the peak current (maybe as high as
Vboost/Rgate)

I'm going to investigate a higher value and probably polypropylene dielectric too.

and there is fuck all inductance in the gatedrive loops.

This one that bothers me. How distant would you suggest the IR211 should be from the
power devices max ?

Tried to minimise the gate drive tracks and indeed all fast tracks but I reckon
my layout man could have done a little better.

I do the layouts myself. far easier.

Well, I supervise but sometimes the layout guy gets carried away when I'm not around.

They have a cruddy CAD ( Vutrax ) system and I'm blowed if I'm learning it when we're
looking at junking it.

it can be a good idea with bootstrap supplies to use a couple of volts
more than the lower supply, because of the load-dependant voltage drop
across the lower switch (and, of course, the diode).


Hmmm........ typical bootstrap operation results in a diode drop plus device > Vce
or Vds drop.

yep. dont forget to check your diode forward recovery time as well. that
can bite a chunk off your supply.

In the bootstrap supply it's a UF4004.

I had to solve a non-regulating flyback supply once (with TL431 + opto
feedback) that in large part was due to the use of a seriously shit
diode for a rectifier (I forget which diode, almost 1N400x type, Trr was
a us or two). I had worked on some of the designers other stuff, didnt
recognise the part number so just assumed he would use a suitable part.
there were other serious problems too, but the diode made me waste a few
days. both forward and reverse recovery were problematic.

I had a sub-contractor supply my first 'proper' flyback supply with a 1N4004 fitted
where there should have been a UF4004. Luckily on an aux rail so the thing was stable.
The 1N4004 fried in due course naturally.

It became a production problem because the output voltage just happened
to be right (ish, calibrate on test) when fed from 115Vac. problem was
it was a universal ac input ups battery charger, and batteries started
dying.....


I'm erring towards local bootstrap supply now.


I presume your diode is a fast HV diode.


MUR 460 in parallel with the switch. ~50ns

que? bootstrap diode (havent read IR2110 data sheet, it may include
them) from -Vdc bias supply to flating supply, cap to E, current
flows when lower switch turns on.

I got at cross purposes there. UF4004 as mentioned above.

I've been using both FETs and IGBTs as the power switches. Some of the IGBTs don't
have internal reverse diodes. So there's an external c-e MUR460 there too. 4A - 50ns -
600V

Cheers, Graham

 

[Pooh Bear]

R Adsett wrote:

In article <42A8F5D9.7D571642@hotmail.com>,
rabbitsfriendsandrelations@hotmail.com says...
Terry Given wrote:

Pooh Bear wrote:

what caps are you using for your bootstrap supplies?

Box polyester film. You gonna say I should be using ceramic ?

Add a electrolytic of some sort for long term hold up if the high sides
are going to be on for a while.

Ton is 4.5us typ.

I don't see whyhaving the FETs turn off when the power goes low is an
issue though. Hmm, unless they are oscillating on/off at high frequency
as the power is sagging. I didn't think the 2110s were prone to that
but...

As the supply sags I see some very odd duty cycles coming out of the driver
stage. I'll definitely add my own UVLO to stop this dead.

Graham

 

[Joerg]

Hello Graham,

Hah - I used some diode ORing on the separate plug-in pcb that has supervisory
stuff. It works fine !

Done it, too, with ye olde BAV70.

Regards, Joerg

http://www.analogconsultants.com

 

[Pooh Bear]

Winfield Hill wrote:

I think you're going down the wrong track. If a FET fails to turn
on because of an activated UV lockout, this should not be the cause
of a MOSFET short. What would be the mechanism for that? Yes, the
desired switching function is interrupted, but benignly so.

OK - it is a bit of a puzzle.

I suspect you have a different common and deadly problem, namely
fast MOSFET source-voltage spikes from reverse-recovery-time
snapoff. This occurs if the FET's intrinsic body diode conducts,
and the ns spikes can damage the FET's delicate gate insulation.
V = L di/dt where L is your FET's source-lead inductance, and the
di/dt is high because dt can be under 1ns during t_rr snapoff.

I should point out that I've been using both FETs and IGBTs and seen the
same effect.

In all failure cases the gate has shorted to the rest of the device though.

Don't know enough about " reverse-recovery-time snapoff ". Could you
elaborate ?

The FET diode's will clamp the flyback from your transformer's
leakage inductance if during the delay after the other FET turns
off the flyback voltage swing is high enough. This clamping with
the resultant spike will happen if you have an inadequate snubbing
network across the FETs to prevent the flyback from swinging across
your entire raw dc voltage supply.

It doesn't. It's quite benign. Really slow in fact. In another test with a
resitive load made of wirewound Rs it gets to maybe 70 - 80 % of supply
before ringing.

The snubber network can simply
be a drain-source capacitor, to absorb the leakage-inductance energy
or it can be more complex. But whatever your choice, don't ever let
the FET's body diodes conduct!!!

You mean don't let the body diode of the FET / IGBT that's just about to
turn on conduct ? I can see that might be bad.

I've been careful to look at the dV/dt at switch off and make sure it's
under control. IGBTs make this easy on account of tail current.

Note, the transformer's leakage-inductance energy is proportional
to current, which means it's flyback effect is minimal under no
load, and worst under full load. Carefully examine your switching
waveforms to see how they change as you increase the load on the
transformer output.

No load yet ! I'm taking this very much bit by bit. In this application
there are instances where there will be no effective load to talk of - so
I'm simply driving the magnetising inductance at present ( or a resistor ).

BTW, did you tell us what FETs you're using? And tell us more
about your transformer and the operating voltages and currents.
Did you measure the transformer's leakage inductance?

I've tried several. One IGBT I've been using is the Infineon SGW30N60. One
of the FETs was also Infineon - one of their CoolMos range a SPW20N60C3
IIRC.

Vbus is 320V @ normal line.

Transformer used is an ETD49 core in N87 (oh no 3C90 - similar - couldn't
get the Epcos core from Farnell ). Pri turns are 16. I.e. 10V / turn - this
works out similar to my observations on a well known design by a major audio
mfr.


Cheers, Graham

 

[Terry Given]

Pooh Bear wrote:

R Adsett wrote:


In article <42A8F5D9.7D571642@hotmail.com>,
rabbitsfriendsandrelations@hotmail.com says...

Terry Given wrote:


Pooh Bear wrote:

what caps are you using for your bootstrap supplies?

Box polyester film. You gonna say I should be using ceramic ?

Add a electrolytic of some sort for long term hold up if the high sides
are going to be on for a while.


Ton is 4.5us typ.


I don't see whyhaving the FETs turn off when the power goes low is an
issue though. Hmm, unless they are oscillating on/off at high frequency
as the power is sagging. I didn't think the 2110s were prone to that
but...


As the supply sags I see some very odd duty cycles coming out of the driver
stage. I'll definitely add my own UVLO to stop this dead.

Graham

Excellent, start-up and shut-down behaviour really requires close
attention. slowly ramping supply rails can uncover a variety of nasties.


Cheers
Terry

 

[Terry Given]

Pooh Bear wrote:

make sure there isnt too much ESR, the capacitance is stable with
voltage & temperature, its happy with the peak current (maybe as high as
Vboost/Rgate)

I'm going to investigate a higher value and probably polypropylene dielectric too.

and there is fuck all inductance in the gatedrive loops.


This one that bothers me. How distant would you suggest the IR211 should be from the
power devices max ?

its not the distance, its the inductance, so minimise the total loop
area the current flows in. My gate drives have a solid return plane
under the entire circuit, connected to the emitter(source) [usually to
the gate drive kelvin connection]. I use a wide conductor for the gate,
and place the final emitter follower + bypass caps + gate resistor
network as close as possible to the gate connection.

Lg serves to increase Rg whenever miller capacitance pumps current into
the gate. this makes the gatedrive less stiff, so Vg will have a wider
flat spot, switching times increase and, if Lg is too large, Vg may rise
high enough to poke a hole in the gate oxide.

look at the Lg-Rg-Cg resonant circuit too, and keep Q low - a bit of
resonant peaking is another good way to poke a hole in the gate oxide.

say 5R and 1nF. for Z=5R L = 25nH. 100nH will have Q=2

Tried to minimise the gate drive tracks and indeed all fast tracks but I reckon
my layout man could have done a little better.

I do the layouts myself. far easier.

Well, I supervise but sometimes the layout guy gets carried away when I'm not around.

They have a cruddy CAD ( Vutrax ) system and I'm blowed if I'm learning it when we're
looking at junking it.

fair enough. I have done the same thing. as long as the
engineer-draughtsman feedback occurs.

if you want to email me a pdf of the layers I can give you my opinion
offline.

it can be a good idea with bootstrap supplies to use a couple of volts
more than the lower supply, because of the load-dependant voltage drop
across the lower switch (and, of course, the diode).


Hmmm........ typical bootstrap operation results in a diode drop plus device > Vce

or Vds drop.

yep. dont forget to check your diode forward recovery time as well. that
can bite a chunk off your supply.


In the bootstrap supply it's a UF4004.

fine.

I had to solve a non-regulating flyback supply once (with TL431 + opto
feedback) that in large part was due to the use of a seriously shit
diode for a rectifier (I forget which diode, almost 1N400x type, Trr was
a us or two). I had worked on some of the designers other stuff, didnt
recognise the part number so just assumed he would use a suitable part.
there were other serious problems too, but the diode made me waste a few
days. both forward and reverse recovery were problematic.


I had a sub-contractor supply my first 'proper' flyback supply with a 1N4004 fitted
where there should have been a UF4004. Luckily on an aux rail so the thing was stable.
The 1N4004 fried in due course naturally.

ayup. I made a lot of money out of that as a tech once, I contracted to
repair some psu's for $50 each. about 100 of them (3 years worth) had
been "repaired" by another tech a month or two earlier, and they all
crapped out. 1N540x in this case.

[snip]

I got at cross purposes there. UF4004 as mentioned above.

I figured

I've been using both FETs and IGBTs as the power switches. Some of the IGBTs don't
have internal reverse diodes. So there's an external c-e MUR460 there too. 4A - 50ns -
600V

Cheers, Graham

Cheers
Terry

 

[Pooh Bear]

Terry Given wrote:

Pooh Bear wrote:
make sure there isnt too much ESR, the capacitance is stable with
voltage & temperature, its happy with the peak current (maybe as high as
Vboost/Rgate)

I'm going to investigate a higher value and probably polypropylene dielectric too.

and there is fuck all inductance in the gatedrive loops.


This one that bothers me. How distant would you suggest the IR211 should be > from the
power devices max ?

its not the distance, its the inductance, so minimise the total loop
area the current flows in.

Understood. I had to explain loop area ( for entirely different reasons ) to a guy in China
a while back. I doubt my 'layout' guy has entirely optimised this. A return trace right next
to - or mirrored on the other side of the pcb would be ideal would it not ?

My gate drives have a solid return plane
under the entire circuit, connected to the emitter(source) [usually to
the gate drive kelvin connection]. I use a wide conductor for the gate,
and place the final emitter follower + bypass caps + gate resistor
network as close as possible to the gate connection.

Right. I do have the gate R pretty damn close the to the gate. Of course there's no emitter
follower with the IR2110. It has a complementary FET output stage with 2A drive.

Lg serves to increase Rg whenever miller capacitance pumps current into
the gate. this makes the gatedrive less stiff,

Figures.

so Vg will have a wider
flat spot, switching times increase and, if Lg is too large, Vg may rise
high enough to poke a hole in the gate oxide.

look at the Lg-Rg-Cg resonant circuit too, and keep Q low - a bit of
resonant peaking is another good way to poke a hole in the gate oxide.

say 5R and 1nF. for Z=5R L = 25nH. 100nH will have Q=2

So I guess I should take a close look at the Vgs waveform and look for resonances / rise
time ? I believe it's quite benign though. The IR2110 outputs look just like the data sheet.
The rise time is slowed by the gate C nicely. It seems to turn off fast though. But I was
looking at the IR2110 side of my 10R gate R. I'll look the other side next.

Tried to minimise the gate drive tracks and indeed all fast tracks but I reckon
my layout man could have done a little better.

I do the layouts myself. far easier.

Well, I supervise but sometimes the layout guy gets carried away when I'm not > around.

They have a cruddy CAD ( Vutrax ) system and I'm blowed if I'm learning it > when we're
looking at junking it.

fair enough. I have done the same thing. as long as the
engineer-draughtsman feedback occurs.

if you want to email me a pdf of the layers I can give you my opinion
offline.

Sure - could do that. Thanks.

it can be a good idea with bootstrap supplies to use a couple of volts
more than the lower supply, because of the load-dependant voltage drop
across the lower switch (and, of course, the diode).


Hmmm........ typical bootstrap operation results in a diode drop plus device > Vce

or Vds drop.

yep. dont forget to check your diode forward recovery time as well. that
can bite a chunk off your supply.

In the bootstrap supply it's a UF4004.

fine.

I had to solve a non-regulating flyback supply once (with TL431 + opto
feedback) that in large part was due to the use of a seriously shit
diode for a rectifier (I forget which diode, almost 1N400x type, Trr was
a us or two). I had worked on some of the designers other stuff, didnt
recognise the part number so just assumed he would use a suitable part.
there were other serious problems too, but the diode made me waste a few
days. both forward and reverse recovery were problematic.


I had a sub-contractor supply my first 'proper' flyback supply with a 1N4004 > fitted
where there should have been a UF4004. Luckily on an aux rail so the > thing was stable.
The 1N4004 fried in due course naturally.

ayup. I made a lot of money out of that as a tech once, I contracted to
repair some psu's for $50 each. about 100 of them (3 years worth) had
been "repaired" by another tech a month or two earlier, and they all
crapped out. 1N540x in this case.

LOL ! Funny how some ppl keep making the same mistakes !

I got at cross purposes there. UF4004 as mentioned above.

I figured

Thanks for the input, Graham

 

[Pooh Bear]

Terry Given wrote:

Pooh Bear wrote:

As the supply sags I see some very odd duty cycles coming out of the driver
stage. I'll definitely add my own UVLO to stop this dead.

Graham

Excellent, start-up and shut-down behaviour really requires close
attention. slowly ramping supply rails can uncover a variety of nasties.

I could almost have missed this if my supervisory supply had not been for
simplicity a transformer, rectifier, C type.

I'm quite pleased in a way that this showed certain odd behaviour. I can take
account of it and eliminate it. Nothing worse than having something in production
that has say problems at low line voltage and you never saw it in development.

Graham

 

[Pooh Bear]

Joerg wrote:

Hello Graham,

Hah - I used some diode ORing on the separate plug-in pcb that has supervisory
stuff. It works fine !

Done it, too, with ye olde BAV70.

Oohh ! BAVs ! Just 1N914 / 4148 / 4448s here.

I do like the BAV21 for higher voltages though.

Graham

 

[R Adsett]

In article <42AB8A53.1AB0CC19@hotmail.com>,
rabbitsfriendsandrelations@hotmail.com says...

R Adsett wrote:

In article <42A8F5D9.7D571642@hotmail.com>,
rabbitsfriendsandrelations@hotmail.com says...
Terry Given wrote:

Pooh Bear wrote:

what caps are you using for your bootstrap supplies?

Box polyester film. You gonna say I should be using ceramic ?

Add a electrolytic of some sort for long term hold up if the high sides
are going to be on for a while.

Ton is 4.5us typ.

Quite fast, 1 uF should be enough. Heck you should be able to get away
with 0.1uF. It will depend on you gate charge a bit though. Also, of
course, on how many FETs you are driving.

I don't see whyhaving the FETs turn off when the power goes low is an
issue though. Hmm, unless they are oscillating on/off at high frequency
as the power is sagging. I didn't think the 2110s were prone to that
but...

As the supply sags I see some very odd duty cycles coming out of the driver
stage. I'll definitely add my own UVLO to stop this dead.

A larger bootstrap cap will also make your high side power supply more
stable and maybe tame your UVLO a bit.

Take a look at you gate drive, at the FET not the 2110, to make sure it's
behaving.


Robert

 

[Terry Given]

Pooh Bear wrote:

Winfield Hill wrote:


I think you're going down the wrong track. If a FET fails to turn
on because of an activated UV lockout, this should not be the cause
of a MOSFET short. What would be the mechanism for that? Yes, the
desired switching function is interrupted, but benignly so.


OK - it is a bit of a puzzle.



I suspect you have a different common and deadly problem, namely
fast MOSFET source-voltage spikes from reverse-recovery-time
snapoff. This occurs if the FET's intrinsic body diode conducts,
and the ns spikes can damage the FET's delicate gate insulation.
V = L di/dt where L is your FET's source-lead inductance, and the
di/dt is high because dt can be under 1ns during t_rr snapoff.


I should point out that I've been using both FETs and IGBTs and seen the
same effect.

this suggests either/or a gatedrive/layout problem.

In all failure cases the gate has shorted to the rest of the device though.

Don't know enough about " reverse-recovery-time snapoff ". Could you
elaborate ?

look at a reverse recovery curve. usually approximated as a triangle,
current ramps negative at some -dI/dt, for some time. Then, it abruptly
reverses and rapidly heads to zero, at a much higher +dI/dt. IIRC the
change of slope of dI/dt can be extremely fast, hence "soft recovery"
diodes.

It is this much-higher-than-expected dI/dt flowing thru stray L that
causes significant voltages where you least expect them.

Likewise the half-bridge-to-reservoir-cap inductance dictates the
reliability of the half-bridge. IGBTs really dont like over-voltages,
and tend to die. A simple test is to use 1200V IGBTs, and if the
failures disappear then its C-E overvoltages doing the damage.

fault conditions are often a killer here. an IGBT will limit to about
10x rated current and desat under a fault condition. but dI/dt just got
10x bigger, so the 25V spike you were happy with just became 250V - kaboom.

your circuit model should include the stray Ls. often you can calculate
the values quite accurately (10%) from the pcb geometry. it is also
worth asking the converse question: for this L here, what is "too much"
voltage, and what dI/dt is required to cause it.

With spice it is easy to use a "spray-can" of inductance - get your
simulation functioning, then at various points add series L, stepping
values to see when problems appear. that'll highlight the areas where
you need to be most careful, but for a half bridge its the bridge-dc bus
cap loop and the individual G-E loops.

Calculations are often not necessary. Obsess about reducing the
inductances at the layout stage, and many problems simply fail to appear.

The FET diode's will clamp the flyback from your transformer's
leakage inductance if during the delay after the other FET turns
off the flyback voltage swing is high enough. This clamping with
the resultant spike will happen if you have an inadequate snubbing
network across the FETs to prevent the flyback from swinging across
your entire raw dc voltage supply.


It doesn't. It's quite benign. Really slow in fact. In another test with a
resitive load made of wirewound Rs it gets to maybe 70 - 80 % of supply
before ringing.


The snubber network can simply
be a drain-source capacitor, to absorb the leakage-inductance energy
or it can be more complex. But whatever your choice, don't ever let
the FET's body diodes conduct!!!


You mean don't let the body diode of the FET / IGBT that's just about to
turn on conduct ? I can see that might be bad.

I've been careful to look at the dV/dt at switch off and make sure it's
under control. IGBTs make this easy on account of tail current.


Note, the transformer's leakage-inductance energy is proportional
to current, which means it's flyback effect is minimal under no
load, and worst under full load. Carefully examine your switching
waveforms to see how they change as you increase the load on the
transformer output.


No load yet ! I'm taking this very much bit by bit. In this application
there are instances where there will be no effective load to talk of - so
I'm simply driving the magnetising inductance at present ( or a resistor ).



BTW, did you tell us what FETs you're using? And tell us more
about your transformer and the operating voltages and currents.
Did you measure the transformer's leakage inductance?


I've tried several. One IGBT I've been using is the Infineon SGW30N60. One
of the FETs was also Infineon - one of their CoolMos range a SPW20N60C3
IIRC.

Vbus is 320V @ normal line.

Transformer used is an ETD49 core in N87 (oh no 3C90 - similar - couldn't
get the Epcos core from Farnell ). Pri turns are 16. I.e. 10V / turn - this
works out similar to my observations on a well known design by a major audio
mfr.


Cheers, Graham

I'm not sure if you have a half- or full-bridge converter.

Al = 4.2uH typ, 3.15uH min, 5.25uH max

Lp = 806uH ~ 1344uH use 800uH

V = 320V
Ton = 4.5us
Aemin = 209mm^2

Bpp = 320V*4.5us = 430mT (full bridge)
-----------
16*209mm^2

so about +/-215mT. Note that the first time you turn it on, Ton better
be less than 4.5us or B will try to ramp up to +430mT and the core will
saturate. Peak Current-Mode Control will do this automatically, *but*
dI/dt can be pretty high, so loop delays (comparator, gatedrive, FET
etc) can really hurt. I would be tempted to have a few more turns, and
keep Bpp below 330mT so that saturation cannot occur (other than by
heating to Tcurie >= 220C).

if its a half bridge, then Bpp = 215mT and the turn-on problem isnt there.

Imagpp = 320V*4.5us = 1.8A max, 1.1A min
----------
800uH

thats pretty high for a full bridge. for a half bridge, its 0.9A and
0.6A respectively.

215mT peak at 100kHz gives 500kW/m^3 for 3C90, about 12W of core loss.
Its gotta be a half-bridge...

108mT peak at 100kHz gives 70kW/m^3 for 3C90, about 1.7W of core loss.

Its a half-bridge, in which case the numbers work out pretty good.

what are the secondaries - 5T+5T centre-tapped?

have you interleaved the windings?

Cheers
Terry

 

[Terry Given]

Pooh Bear wrote:
[snip]

its not the distance, its the inductance, so minimise the total loop
area the current flows in.

Understood. I had to explain loop area ( for entirely different reasons ) to a guy in China
a while back. I doubt my 'layout' guy has entirely optimised this. A return trace right next
to - or mirrored on the other side of the pcb would be ideal would it not ?

I figured you did.

My gate drives have a solid return plane
under the entire circuit, connected to the emitter(source) [usually to
the gate drive kelvin connection]. I use a wide conductor for the gate,
and place the final emitter follower + bypass caps + gate resistor
network as close as possible to the gate connection.

Right. I do have the gate R pretty damn close the to the gate. Of course there's no emitter
follower with the IR2110. It has a complementary FET output stage with 2A drive.

it might still be piss-weak - 12V/2A = 6 Ohms. drive a known capacitor,
and measure the rise & fall times. A resistive load is useful too.

Lg serves to increase Rg whenever miller capacitance pumps current into
the gate. this makes the gatedrive less stiff,

Figures.

the logical conclusion: look into the gatedrive, thru the output stage,
around to the reservoir cap and back to the FET.

Its easy to mount FETs so as to maximise the TOxxx lead length,
helpfully doubling or even tripling the internal package inductance.

so Vg will have a wider
flat spot, switching times increase and, if Lg is too large, Vg may rise
high enough to poke a hole in the gate oxide.

look at the Lg-Rg-Cg resonant circuit too, and keep Q low - a bit of
resonant peaking is another good way to poke a hole in the gate oxide.

say 5R and 1nF. for Z=5R L = 25nH. 100nH will have Q=2


So I guess I should take a close look at the Vgs waveform and look for resonances / rise
time ? I believe it's quite benign though. The IR2110 outputs look just like the data sheet.
The rise time is slowed by the gate C nicely. It seems to turn off fast though. But I was
looking at the IR2110 side of my 10R gate R. I'll look the other side next.

you probably have an over-damped system. The FET/IGBT will have its own
gate resistance (and inductance) too. this means the gate drive itself
wont automatically kill the gate, *but* excess Rg increases the
impedance seen by the gate, a-la miller etc. I tend to minimise L by
layout, then select Rg on test for critical damping.

Tried to minimise the gate drive tracks and indeed all fast tracks but I reckon
my layout man could have done a little better.

I do the layouts myself. far easier.

Well, I supervise but sometimes the layout guy gets carried away when I'm not > around.

They have a cruddy CAD ( Vutrax ) system and I'm blowed if I'm learning it > when we're

looking at junking it.

fair enough. I have done the same thing. as long as the
engineer-draughtsman feedback occurs.

if you want to email me a pdf of the layers I can give you my opinion
offline.


Sure - could do that. Thanks.

no worries.

it can be a good idea with bootstrap supplies to use a couple of volts
more than the lower supply, because of the load-dependant voltage drop
across the lower switch (and, of course, the diode).


Hmmm........ typical bootstrap operation results in a diode drop plus device > Vce

or Vds drop.

yep. dont forget to check your diode forward recovery time as well. that
can bite a chunk off your supply.

In the bootstrap supply it's a UF4004.

fine.


I had to solve a non-regulating flyback supply once (with TL431 + opto
feedback) that in large part was due to the use of a seriously shit
diode for a rectifier (I forget which diode, almost 1N400x type, Trr was
a us or two). I had worked on some of the designers other stuff, didnt
recognise the part number so just assumed he would use a suitable part.
there were other serious problems too, but the diode made me waste a few
days. both forward and reverse recovery were problematic.


I had a sub-contractor supply my first 'proper' flyback supply with a 1N4004 > fitted

where there should have been a UF4004. Luckily on an aux rail so the > thing was stable.
The 1N4004 fried in due course naturally.

ayup. I made a lot of money out of that as a tech once, I contracted to
repair some psu's for $50 each. about 100 of them (3 years worth) had
been "repaired" by another tech a month or two earlier, and they all
crapped out. 1N540x in this case.


LOL ! Funny how some ppl keep making the same mistakes !

everything is difficult until you learn how

I got at cross purposes there. UF4004 as mentioned above.

I figured


Thanks for the input, Graham

Cheers
Terry

 

[Terry Given]

Pooh Bear wrote:

Terry Given wrote:


Pooh Bear wrote:


As the supply sags I see some very odd duty cycles coming out of the driver
stage. I'll definitely add my own UVLO to stop this dead.

Graham

Excellent, start-up and shut-down behaviour really requires close
attention. slowly ramping supply rails can uncover a variety of nasties.


I could almost have missed this if my supervisory supply had not been for
simplicity a transformer, rectifier, C type.

I'm quite pleased in a way that this showed certain odd behaviour. I can take
account of it and eliminate it. Nothing worse than having something in production
that has say problems at low line voltage and you never saw it in development.

Graham

self-oscillating flyback converters are good too - the gate drive is
generated by a flyback winding, so isnt there at all at power-up, and
slowly ramps up in accordance with the output voltage rising. so gate
drive starts out nonexistent, then slowly (ms) ramps through the
threshold region. that can frighten the piss out of the switching
transistor.

flyback battery chargers are likewise problematic - a flat battery can
reduce the bias supply voltage, making the smps hiccup or even go bang.

As long as you ensure your gate voltages are well regulated, from
open-circuit to short-circuit. which is where a decent UVLO comes in.
With bootstrap supplies, you also may need to "energise" them prior to
starting (in an AC drive running at low speed, alternating zero vectors
will keep them charged).

I learned a good trick from a guy at DG, which is to ramp input voltage
from 0 to Vmax and back to 0 again at 1V/s.

Cheers
Terry

 

[Pooh Bear]

R Adsett wrote:

In article <42AB8A53.1AB0CC19@hotmail.com>,
rabbitsfriendsandrelations@hotmail.com says...
R Adsett wrote:

In article <42A8F5D9.7D571642@hotmail.com>,
rabbitsfriendsandrelations@hotmail.com says...
Terry Given wrote:

Pooh Bear wrote:

what caps are you using for your bootstrap supplies?

Box polyester film. You gonna say I should be using ceramic ?

Add a electrolytic of some sort for long term hold up if the high sides
are going to be on for a while.

Ton is 4.5us typ.

Quite fast, 1 uF should be enough. Heck you should be able to get away
with 0.1uF. It will depend on you gate charge a bit though. Also, of
course, on how many FETs you are driving.

Looking at a similar design, they use 0.2uF. I have too. Ciss is 1900pF typical
for my preferred device. Just the single device.

I don't see whyhaving the FETs turn off when the power goes low is an
issue though. Hmm, unless they are oscillating on/off at high frequency
as the power is sagging. I didn't think the 2110s were prone to that
but...

As the supply sags I see some very odd duty cycles coming out of the driver
stage. I'll definitely add my own UVLO to stop this dead.

A larger bootstrap cap will also make your high side power supply more
stable and maybe tame your UVLO a bit.

I'll do that ( make it bigger - can't do any harm ! ).

Take a look at you gate drive, at the FET not the 2110, to make sure it's
behaving.

Ah well - it's just the other side of the 10R ! Yes - I'll investigate.

Graham

 

[Pooh Bear]

Terry Given wrote:

Pooh Bear wrote:

I'm quite pleased in a way that this showed certain odd behaviour. I can take
account of it and eliminate it. Nothing worse than having something in > production
that has say problems at low line voltage and you never saw it in > development.

Graham

self-oscillating flyback converters are good too - the gate drive is
generated by a flyback winding, so isnt there at all at power-up, and
slowly ramps up in accordance with the output voltage rising. so gate
drive starts out nonexistent, then slowly (ms) ramps through the
threshold region. that can frighten the piss out of the switching
transistor.

That reminds me of an apochryphal story about a supposed WWI de-lousing machine. You
were supposed to pass your garments through it but it had no useful effect. In return
the supposed comment was " I expect it gave them a damn good fright though ! ".

flyback battery chargers are likewise problematic - a flat battery can
reduce the bias supply voltage, making the smps hiccup or even go bang.

As long as you ensure your gate voltages are well regulated, from
open-circuit to short-circuit. which is where a decent UVLO comes in.

Point taken.

With bootstrap supplies, you also may need to "energise" them prior to
starting (in an AC drive running at low speed, alternating zero vectors
will keep them charged).

Yup. I'm inclined to run Vboot from a separate oscillator. That way it won't be
affected by Vce sat either.

I learned a good trick from a guy at DG, which is to ramp input voltage
from 0 to Vmax and back to 0 again at 1V/s.

I was indeed 'inching' my variac to view the various odd modes of behaviour. Very
entertaining. Stuff happens that isn't on the data sheet.

Graham