R
Rick C
Guest
Looking for a good way to support initialized block rams in my design I found that VHDL-2008 includes some new predefined array types such as integer_vector, an array of integers.
Integers are either 32 or even 64 bits, so that would be a rather wide memory. Is there a way to restrict the range of the integer of such an array?
I\'d like to have a single file for the definition of a block ram because it will require a synthesis attribute which likely won\'t port well. So rather than scatter this issue around the design, a single module seems like a good idea. The memory module also needs to support initialization. Not sure of the best way to support that. I\'m thinking a constant array passed in through a generic.
I\'m still fuzzy on the details of how to make this all work together. I guess I could have a file with the constant array definition. Then the application code can instantiate the memory array with the constant initialization array as a generic.
I\'ve always heard that memory is best written as an array of integers for simulation efficiency. But that requires limiting the range of the integer. If the integer_vector type is used it would seem the word size is fixed at whatever the synthesis vendor provides in their defaults. Or is there a way to restrict the range of the integers without a special type for each width?
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209
Integers are either 32 or even 64 bits, so that would be a rather wide memory. Is there a way to restrict the range of the integer of such an array?
I\'d like to have a single file for the definition of a block ram because it will require a synthesis attribute which likely won\'t port well. So rather than scatter this issue around the design, a single module seems like a good idea. The memory module also needs to support initialization. Not sure of the best way to support that. I\'m thinking a constant array passed in through a generic.
I\'m still fuzzy on the details of how to make this all work together. I guess I could have a file with the constant array definition. Then the application code can instantiate the memory array with the constant initialization array as a generic.
I\'ve always heard that memory is best written as an array of integers for simulation efficiency. But that requires limiting the range of the integer. If the integer_vector type is used it would seem the word size is fixed at whatever the synthesis vendor provides in their defaults. Or is there a way to restrict the range of the integers without a special type for each width?
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209