J
James Williams
Guest
Hello,
I am just now learning VHDL and am wondering how I work write code to use
one single 8bit in/out pins, which is mapped to 4 internal 8bit registers,
which can either be read or written too. It of course would has a 2 bit
address select. I know how to do the entity declaration, I'm not quite sure
how to do the arch process. Here is what I am thinking, please tell me if I
am doing this wrong.
Note also that this is just an example on not my actual project.
entity myMemory is
port (Clk : in std_logic;
DataIo :inout std_logic_vector (7 downto 0) Bus :=(others=>'Z');
OutEn : in std_logic_vector; --Enables the output buffers.
Write : in std_logic; --Write to memory " Active low"
Read : in std_logic; --Read from memory "Active low"
Addr : in std_logic_vector (1 downto 0));
end myMemory;
architecture Behavioral of myMemory is
signal Reg0 : std_logic_vector (7 downto 0);
signal Reg1 : std_logic_vector (7 downto 0);
signal Reg2 : std_logic_vector (7 downto 0);
signal Reg3 : std_logic_vector (7 downto 0);
begin
process(Clk) begin
if(Clk'event and Clk='1') then
case Addr is
when "00"=>
if(Read='0' and Write='1' and 'OutEn='1') then
DataIo<=Reg0;
elsif (Read='1' and Write='0' and OutEn='X') then
Reg0<=DataIo;
else DataIo<=(others=>'Z');
when "01"=>
if(Read='0' and Write='1' and 'OutEn='1') then
DataIo<=Reg1;
elsif (Read='1' and Write='0' and OutEn='X') then
Reg1<=DataIo;
else DataIo<=(others=>'Z');
when "10"=>
if(Read='0' and Write='1' and 'OutEn='1') then
DataIo<=Reg2;
elsif (Read='1' and Write='0' and OutEn='X') then
Reg2<=DataIo;
else DataIo<=(others=>'Z');
when "11"=>
if(Read='0' and Write='1' and 'OutEn='1') then
DataIo<=Reg3;
elsif (Read='1' and Write='0' and OutEn='X') then
Reg3<=DataIo;
else DataIo<=(others=>'Z');
when others =>
if(OutEn='0' then DataIo<=(others=>'Z');
end if;
end case;
end if;
end process;
end Behavioral;
I am just now learning VHDL and am wondering how I work write code to use
one single 8bit in/out pins, which is mapped to 4 internal 8bit registers,
which can either be read or written too. It of course would has a 2 bit
address select. I know how to do the entity declaration, I'm not quite sure
how to do the arch process. Here is what I am thinking, please tell me if I
am doing this wrong.
Note also that this is just an example on not my actual project.
entity myMemory is
port (Clk : in std_logic;
DataIo :inout std_logic_vector (7 downto 0) Bus :=(others=>'Z');
OutEn : in std_logic_vector; --Enables the output buffers.
Write : in std_logic; --Write to memory " Active low"
Read : in std_logic; --Read from memory "Active low"
Addr : in std_logic_vector (1 downto 0));
end myMemory;
architecture Behavioral of myMemory is
signal Reg0 : std_logic_vector (7 downto 0);
signal Reg1 : std_logic_vector (7 downto 0);
signal Reg2 : std_logic_vector (7 downto 0);
signal Reg3 : std_logic_vector (7 downto 0);
begin
process(Clk) begin
if(Clk'event and Clk='1') then
case Addr is
when "00"=>
if(Read='0' and Write='1' and 'OutEn='1') then
DataIo<=Reg0;
elsif (Read='1' and Write='0' and OutEn='X') then
Reg0<=DataIo;
else DataIo<=(others=>'Z');
when "01"=>
if(Read='0' and Write='1' and 'OutEn='1') then
DataIo<=Reg1;
elsif (Read='1' and Write='0' and OutEn='X') then
Reg1<=DataIo;
else DataIo<=(others=>'Z');
when "10"=>
if(Read='0' and Write='1' and 'OutEn='1') then
DataIo<=Reg2;
elsif (Read='1' and Write='0' and OutEn='X') then
Reg2<=DataIo;
else DataIo<=(others=>'Z');
when "11"=>
if(Read='0' and Write='1' and 'OutEn='1') then
DataIo<=Reg3;
elsif (Read='1' and Write='0' and OutEn='X') then
Reg3<=DataIo;
else DataIo<=(others=>'Z');
when others =>
if(OutEn='0' then DataIo<=(others=>'Z');
end if;
end case;
end if;
end process;
end Behavioral;