how to generate random time delays for simulation during com

I have ring oscilator design, I am generating 32 ring oscillators using following code. How can I generate random time delays instead of loop variable "i"? (I am sorry for code, it doesn't look like code formatted, I am writing this post from mobile browser)

for i in 0 to nr_entries-1 generate
multiple_n: w_entity
generic map (delay => (i+1) * 1 ps , chain_len => nr_chains) -- delay must be "random" from 100 to 300 ps
port map (
rst_i => s_rst,
out_o => s_inp(i)
);
end generate;

 

[Leonardo Capossio]

El martes, 26 de mayo de 2015, 1:33:25 (UTC-3), mubin...@gmail.com escribió:

I have ring oscilator design, I am generating 32 ring oscillators using following code. How can I generate random time delays instead of loop variable "i"? (I am sorry for code, it doesn't look like code formatted, I am writing this post from mobile browser)

for i in 0 to nr_entries-1 generate
multiple_n: w_entity
generic map (delay => (i+1) * 1 ps , chain_len => nr_chains) -- delay must be "random" from 100 to 300 ps
port map (
rst_i => s_rst,
out_o => s_inp(i)
);
end generate;

A well known trick, a quick search returns:

http://vhdlguru.blogspot.com.ar/2013/08/generating-random-numbers-in-vhdl.html

 

[Nicolas Matringe]

Le 26/05/2015 22:12, Leonardo Capossio a ĂŠcrit :

El martes, 26 de mayo de 2015, 1:33:25 (UTC-3), mubin...@gmail.com escribiĂł:
I have ring oscilator design, I am generating 32 ring oscillators using following code. How can I generate random time delays instead of loop variable "i"? (I am sorry for code, it doesn't look like code formatted, I am writing this post from mobile browser)

for i in 0 to nr_entries-1 generate
multiple_n: w_entity
generic map (delay => (i+1) * 1 ps , chain_len => nr_chains) -- delay must be "random" from 100 to 300 ps
port map (
rst_i => s_rst,
out_o => s_inp(i)
);
end generate;

A well known trick, a quick search returns:
http://vhdlguru.blogspot.com.ar/2013/08/generating-random-numbers-in-vhdl.html

Very nice but it won't work for a generic parameter, as requested by the
original poster.

It is probably possible to use the UNIFORM procedure from the math_real
package to generate pseudo-random numbers inside the for...generate loop.

Nicolas

 

[Andy]

Take a look at Open Source VHDL Verification Methodology (osvvm.org).

It provides constrained randomization, coverage modeling and more.

You need to declare constant(s) initialized by function calls, then map the generics to the constants.

Andy