How to extend a pulse width without clock!

[peterzhu]

Due to a chip bug, I have to extend a pulse width(negative)from 10ns
to 100ms in CPLD(Altera 7128). But the difficult is that I have no any
clock into the CPLD, so the CPLD is pure combination logic. how to
extend it in such case?

Help me!

 

[Simon Peacock]

Am not sure you can.. all the logic on the chip can't generate that kind of
delay.. but you might find another signal which you can use as a clock A0
if you have a micro.. or ALE.. WR.. RD something like that.. failing that..
an RC off chip

Simon


"peterzhu" <peter.zhu@utstar.com> wrote in message
news:61c1427f.0309030030.57cc99c4@posting.google.com...

Due to a chip bug, I have to extend a pulse width(negative)from 10ns
to 100ms in CPLD(Altera 7128). But the difficult is that I have no any
clock into the CPLD, so the CPLD is pure combination logic. how to
extend it in such case?

Help me!

 

[Lorenzo]

"peterzhu" <peter.zhu@utstar.com> ha scritto nel messaggio
news:61c1427f.0309030030.57cc99c4@posting.google.com...

Due to a chip bug, I have to extend a pulse
width(negative)from 10ns
to 100ms in CPLD(Altera 7128).

Can you add some very small components? You can build a very simple
monostable by connecting a RC network between two CPLD pins.

--
Lorenzo

 

[Antti Lukats]

"peterzhu" <peter.zhu@utstar.com> wrote in message
news:61c1427f.0309030030.57cc99c4@posting.google.com...
Due to a chip bug, I have to extend a pulse width(negative)from 10ns
to 100ms in CPLD(Altera 7128). But the difficult is that I have no any
clock into the CPLD, so the CPLD is pure combination logic. how to
extend it in such case?

uups, bad luck - not recommended but if you have enough free pins and logic
you and if the timing is not critical it is possible to make free running
oscillator without external RC components, just connect uneven count of
inverters in ring (ie 3 inverters) as this is astable it will oscillate
with pretty high frequency, this could be divided down, but from about
40MHz down to 100ms its pretty long counter ... and this approuch
really isnt 'recommended'

as other options build simple RC on IO cells and use that signal

antti