Help with Laplace Transform for PLL VCO, Kvco?????

Dr. Slick · Mar 17, 2004

Hello,

I've been interested in the Phase locked loop for some time
now, and something has always got me wondering.

Why do they have the 1/s (s is the complex variable in Laplace
and
is equal to jw) for the transfer function of the Voltage controlled
oscillator?

I understand that the Kvco is usually in MHz/volt, but could
someone explain why it has the 1/s? Which indicates that the transfer
function goes to infinity at DC (0 Hz)?

My guess today has been that the tuning voltage can be at a DC
voltage (like a single phase), and yet the phase of the output
continues to increase, which kinda implies that the Output phi/Input
phi gain is infinite.

Any educated comments?

Slick

Terry Given · Mar 17, 2004

"Dr. Slick" <radio913@aol.com> wrote in message
news:1d15af91.0403162351.57fd1d7e@posting.google.com...

Hello,

I've been interested in the Phase locked loop for some time
now, and something has always got me wondering.

Why do they have the 1/s (s is the complex variable in Laplace
and
is equal to jw) for the transfer function of the Voltage controlled
oscillator?

I understand that the Kvco is usually in MHz/volt, but could
someone explain why it has the 1/s? Which indicates that the transfer
function goes to infinity at DC (0 Hz)?

My guess today has been that the tuning voltage can be at a DC
voltage (like a single phase), and yet the phase of the output
continues to increase, which kinda implies that the Output phi/Input
phi gain is infinite.

Any educated comments?

Phase Locked Loops, R.E. Best, McGraw-Hill

Tim Wescott · Mar 17, 2004

"Dr. Slick" <radio913@aol.com> wrote in message
news:1d15af91.0403162351.57fd1d7e@posting.google.com...

Hello,

I've been interested in the Phase locked loop for some time
now, and something has always got me wondering.

Why do they have the 1/s (s is the complex variable in Laplace
and
is equal to jw) for the transfer function of the Voltage controlled
oscillator?

I understand that the Kvco is usually in MHz/volt, but could
someone explain why it has the 1/s? Which indicates that the transfer
function goes to infinity at DC (0 Hz)?

My guess today has been that the tuning voltage can be at a DC
voltage (like a single phase), and yet the phase of the output
continues to increase, which kinda implies that the Output phi/Input
phi gain is infinite.

Any educated comments?

Slick

"Phase-Locked Loop Circuit Design" by Dan H Wolaver, Prentice-Hall, c 1991.
It's a very good book, he really digs into the practical aspects and
connects them solidly to the theory.

Fred Bloggs · Mar 17, 2004

Dr. Slick wrote:

I understand that the Kvco is usually in MHz/volt, but could
someone explain why it has the 1/s? Which indicates that the transfer
function goes to infinity at DC (0 Hz)?

My guess today has been that the tuning voltage can be at a DC
voltage (like a single phase), and yet the phase of the output
continues to increase, which kinda implies that the Output phi/Input
phi gain is infinite.

Any educated comments?

Well- maybe not an educated comment but certainly an educamated one
(<-not even a sentence). The Laplace transfer modeling of the loop only
applies to a loop in lock- the modeling for out-of-lock conditions,
although tractable, is beyond the comprehension of most. The primary
dependent variable is always phase, the VCO is a voltage-to-frequency
conversion device, frequency is analogous to rate, phase is analogous to
distance, so that phase is therefore frequency-x-time and this abstracts
to phase= time integral of VCO frequency, giving the 1/s correspondence
in the Laplace transform domain. You are right about the infinite
response at DC- going back to the rate/distance analogy- voltages
applied for brief periods result in less distance traveled and voltages
applied for arbitrarily long durations result in arbitrarily long
distances. This is exactly what you want for a closed loop system
because it means the VCO gain is so high that the only final state
possible is one with zero phase error between the VCO and reference input.

John Larkin · Mar 17, 2004

On Wed, 17 Mar 2004 16:12:28 GMT, Fred Bloggs <nospam@nospam.com>
wrote:

because it means the VCO gain is so high that the only final state
possible is one with zero phase error between the VCO and reference input.

Zero frequency error, I think.

John

John Larkin · Mar 18, 2004

On Wed, 17 Mar 2004 22:45:05 -0800, "Terry Given"
<the_domes@xtra.co.nz> wrote:

"Dr. Slick" <radio913@aol.com> wrote in message
news:1d15af91.0403162351.57fd1d7e@posting.google.com...
Hello,

I've been interested in the Phase locked loop for some time
now, and something has always got me wondering.

Why do they have the 1/s (s is the complex variable in Laplace
and
is equal to jw) for the transfer function of the Voltage controlled
oscillator?

I understand that the Kvco is usually in MHz/volt, but could
someone explain why it has the 1/s? Which indicates that the transfer
function goes to infinity at DC (0 Hz)?

My guess today has been that the tuning voltage can be at a DC
voltage (like a single phase), and yet the phase of the output
continues to increase, which kinda implies that the Output phi/Input
phi gain is infinite.

Any educated comments?

Phase Locked Loops, R.E. Best, McGraw-Hill

I have a couple of PLL texts, and none mention bangbang (d-flop) phase
detectors. Does anybody know of books that do?

John

Dr. Slick · Mar 18, 2004

"Terry Given" <the_domes@xtra.co.nz> wrote in message news:<U3V5c.7769$rw6.156556@news.xtra.co.nz>...

I understand that the Kvco is usually in MHz/volt, but could
someone explain why it has the 1/s? Which indicates that the transfer
function goes to infinity at DC (0 Hz)?

My guess today has been that the tuning voltage can be at a DC
voltage (like a single phase), and yet the phase of the output
continues to increase, which kinda implies that the Output phi/Input
phi gain is infinite.

Any educated comments?

Phase Locked Loops, R.E. Best, McGraw-Hill

I've got this book, and he doesn't answer my question, at least not
what i read last night.

S.

hugh.w.p · Mar 18, 2004

"John Larkin" <jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote in
message news:1i4h50lcvc38mfaram1jbjckui1n8ha37f@4ax.com...

On Wed, 17 Mar 2004 22:45:05 -0800, "Terry Given"
the_domes@xtra.co.nz> wrote:

"Dr. Slick" <radio913@aol.com> wrote in message
news:1d15af91.0403162351.57fd1d7e@posting.google.com...
Hello,

I've been interested in the Phase locked loop for some time
now, and something has always got me wondering.

Why do they have the 1/s (s is the complex variable in Laplace
and
is equal to jw) for the transfer function of the Voltage controlled
oscillator?

I understand that the Kvco is usually in MHz/volt, but could
someone explain why it has the 1/s? Which indicates that the transfer
function goes to infinity at DC (0 Hz)?

My guess today has been that the tuning voltage can be at a DC
voltage (like a single phase), and yet the phase of the output
continues to increase, which kinda implies that the Output phi/Input
phi gain is infinite.

Any educated comments?

Phase Locked Loops, R.E. Best, McGraw-Hill

I have a couple of PLL texts, and none mention bangbang (d-flop) phase
detectors. Does anybody know of books that do?

John

are these ones that work on digital signals?. I presume such as floppy disk

data synchronisation etc?

Jim Thompson · Mar 18, 2004

On Wed, 17 Mar 2004 10:05:04 -0800, John Larkin
<jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote:

[snip]

I have a couple of PLL texts, and none mention bangbang (d-flop) phase
detectors. Does anybody know of books that do?

John

I've only heard of two-D-flop configurations that do edge-matching.
I'm guessing that you mean by "bang-bang" those that put one signal on
"CLK" and one on "D"? That configuration is used more often for
harmonic down conversion (see the Moto PECL parts).

Previously I've described here VCOs that were made with
shift-registers driven by a high frequency clock, with phase control
by phase "jerking" (clearing) the S-R.

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice

480)460-2350 | |
| E-mail Address at Website Fax

John Larkin · Mar 18, 2004

On Wed, 17 Mar 2004 13:02:50 -0700, Jim Thompson
<thegreatone@example.com> wrote:

On Wed, 17 Mar 2004 10:05:04 -0800, John Larkin
jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote:

[snip]
I have a couple of PLL texts, and none mention bangbang (d-flop) phase
detectors. Does anybody know of books that do?

John

I've only heard of two-D-flop configurations that do edge-matching.
I'm guessing that you mean by "bang-bang" those that put one signal on
"CLK" and one on "D"? That configuration is used more often for
harmonic down conversion (see the Moto PECL parts).

Right. I invented this in about 1972, although I'm sure somebody else
invented it first; my only real claim here is to ignorance.

I did a timing module for the NIF laser that locks a 155.52 MHz vcxo
to an incoming OC3 optical data stream, and used a single EL51
flip-flop as the phase detecor. I had no good ideas as to a proper
math model for the loop, so made some wild guesses and, with a bit of
tweaking, it worked really good... jitter in the 1 ps RMS range, I
think. I had to switch from acquire mode to track mode to make it lock
and have low jitter.

This detector seems to have infinite gain in a noise-free system, and
roughly Vcc/B phase-voltage slope where B is the actual RMS jitter of
the incoming signal. Or something.

Oh, the EL51 has a picosecond or two of setup/hold hysteresis,
depending on the current 1/0 state of the flop.

John

Bill Sloman · Mar 18, 2004

John Larkin <jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote in message news:<r7vg50924c6n88hb3qea96vr2jt90app6c@4ax.com>...

On Wed, 17 Mar 2004 16:12:28 GMT, Fred Bloggs <nospam@nospam.com
wrote:

because it means the VCO gain is so high that the only final state
possible is one with zero phase error between the VCO and reference input.

Zero frequency error, I think.

Floyd M. Gardner's "Phaselock Techniques" (ISBN 0-471-04294-3)
classifies phase-locked loops as first order if they have zero
frequency error but a finite phase error, second order if they have a
zero phase error at static frequency and third order if they track a
varying frequency with zero phase error.

------
Bill Sloman, Nijmegen

Mike · Mar 18, 2004

On Wed, 17 Mar 2004 10:05:04 -0800, John Larkin wrote:

I have a couple of PLL texts, and none mention bangbang (d-flop) phase
detectors. Does anybody know of books that do?

John

Sure. The latest compilation of papers by Behzad Razavi (Phase-Locking in
High-Performance Systems: From Devices to Architectures - IEEE Press)
contains an invited paper by Rick Walker at HP Labs/Agilent on analysis of
clock recovery circuits using bang-bang phase detectors.

Walker's paper seems to be an expansion of a short course he gave at ISSCC
a few years ago. The short course notes and the paper included in Razavi's
compilation are available on Walker's web site. Walker's approach is to
manipulate the loop until it looks like a sigma-delta modulator, then use
linear sigma-delta analysis.

On the other hand, if what you're interested in is a discussion of
different types of bang-bang phase detectors, check out Razavi's first
compilation on the subject (Monolithic Phase-Locked Loops and Clock
Recovery Circuits). The original papers by Hogge and Alexander are
included, as well as some others.

Jri Lee, Ken Kundert, and Razavi presented a paper on jitter analysis of
bang-bang PLLs at last year's CICC; my understanding is that a
feature-length paper based on that work will be published this summer in
JSSC. My recollection is that they follow Walker's bang-bang loop analysis.

For an entirely different approach, dig up a copy of Thaler and Pastel,
"Analysis and Design of Nonlinear Feedback Control Systems," McGraw-Hill,
1962. They spend a chapter on relay feedback systems, which are entirely
analagous (if not equivalent) to bang-bang phase detectors. Their approach
is mostly graphical, but provides some rather nice insights about limit
cycles and stability. As might be expected, their schematics use things
like motors and relays, not flip-flops. The insightful student can make the
appropriate substitutions.

-- Mike --

Kevin Aylward · Mar 18, 2004

Bill Sloman wrote:

John Larkin <jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote in
message news:<r7vg50924c6n88hb3qea96vr2jt90app6c@4ax.com>...
On Wed, 17 Mar 2004 16:12:28 GMT, Fred Bloggs <nospam@nospam.com
wrote:

because it means the VCO gain is so high that the only final state
possible is one with zero phase error between the VCO and reference
input.

Zero frequency error, I think.

Floyd M. Gardner's "Phaselock Techniques" (ISBN 0-471-04294-3)
classifies phase-locked loops as first order if they have zero
frequency error but a finite phase error, second order if they have a
zero phase error at static frequency and third order if they track a
varying frequency with zero phase error.

Why?

This is misleading or confusing at best. "Order" usually refers to the
total *filter* order. The standard one stage pole-zero LP filter used on
typical PLLs will be stable for *all* of the above phase detectors. They
are all (1+as)/s(1+bs). This is a 2nd order system, compensated to
single at HF. Naming the zero phase error frequency tracking detector
system as a 3rd order system implies that you need two leads to
compensate it, when you most certainly don't.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

Allan Herriman · Mar 18, 2004

On Thu, 18 Mar 2004 09:09:20 -0000, "Kevin Aylward"
<kevindotaylwardEXTRACT@anasoft.co.uk> wrote:

Bill Sloman wrote:
John Larkin <jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote in
message news:<r7vg50924c6n88hb3qea96vr2jt90app6c@4ax.com>...
On Wed, 17 Mar 2004 16:12:28 GMT, Fred Bloggs <nospam@nospam.com
wrote:

because it means the VCO gain is so high that the only final state
possible is one with zero phase error between the VCO and reference
input.

Zero frequency error, I think.

Floyd M. Gardner's "Phaselock Techniques" (ISBN 0-471-04294-3)
classifies phase-locked loops as first order if they have zero
frequency error but a finite phase error, second order if they have a
zero phase error at static frequency and third order if they track a
varying frequency with zero phase error.

Why?

This is misleading or confusing at best. "Order" usually refers to the
total *filter* order.

Kevin, do you have any references to support your claim? I've only
ever seen "order" used to represent the number of open loop poles *of
the entire loop*, not just the filter.

Regards,
Allan.

Fred Bloggs · Mar 18, 2004

John Larkin wrote:

On Wed, 17 Mar 2004 13:02:50 -0700, Jim Thompson
thegreatone@example.com> wrote:

On Wed, 17 Mar 2004 10:05:04 -0800, John Larkin
jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote:

[snip]

I have a couple of PLL texts, and none mention bangbang (d-flop) phase
detectors. Does anybody know of books that do?

John

I've only heard of two-D-flop configurations that do edge-matching.
I'm guessing that you mean by "bang-bang" those that put one signal on
"CLK" and one on "D"? That configuration is used more often for
harmonic down conversion (see the Moto PECL parts).

Right. I invented this in about 1972, although I'm sure somebody else
invented it first; my only real claim here is to ignorance.

I did a timing module for the NIF laser that locks a 155.52 MHz vcxo
to an incoming OC3 optical data stream, and used a single EL51
flip-flop as the phase detecor. I had no good ideas as to a proper
math model for the loop, so made some wild guesses and, with a bit of
tweaking, it worked really good... jitter in the 1 ps RMS range, I
think. I had to switch from acquire mode to track mode to make it lock
and have low jitter.

This detector seems to have infinite gain in a noise-free system, and
roughly Vcc/B phase-voltage slope where B is the actual RMS jitter of
the incoming signal. Or something.

Oh, the EL51 has a picosecond or two of setup/hold hysteresis,
depending on the current 1/0 state of the flop.

John

That is probably a third-order loop in reality because you have the very
high-Q VCXO with response time normalized to many oscillation cycles,
maybe hundreds, being updated on a per-cycle basis by the D-FF error
detector. I think the price you pay is one or two orders of magnitude
higher phase noise as compared to a properly linearized loop- because
you are injecting that large amplitude random bit stream into the
control input.

Kevin Aylward · Mar 18, 2004

Allan Herriman wrote:

On Thu, 18 Mar 2004 09:09:20 -0000, "Kevin Aylward"
kevindotaylwardEXTRACT@anasoft.co.uk> wrote:

Bill Sloman wrote:
John Larkin <jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote in
message news:<r7vg50924c6n88hb3qea96vr2jt90app6c@4ax.com>...
On Wed, 17 Mar 2004 16:12:28 GMT, Fred Bloggs <nospam@nospam.com
wrote:

because it means the VCO gain is so high that the only final state
possible is one with zero phase error between the VCO and
reference input.

Zero frequency error, I think.

Floyd M. Gardner's "Phaselock Techniques" (ISBN 0-471-04294-3)
classifies phase-locked loops as first order if they have zero
frequency error but a finite phase error, second order if they have
a zero phase error at static frequency and third order if they
track a varying frequency with zero phase error.

Why?

This is misleading or confusing at best. "Order" usually refers to
the total *filter* order.

Kevin, do you have any references to support your claim? I've only
ever seen "order" used to represent the number of open loop poles *of
the entire loop*, not just the filter.

That's not what I meant. I admit this was a bit vague. By filter order I
did mean the whole system response. My issue is that the tracking a
varying frequency with zero phase error system is not a 3rd order system
in terms of its loop response. If it was, the PLLs I have designed
simply would not work, they would oscillate.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

John Larkin · Mar 18, 2004

On Thu, 18 Mar 2004 11:41:40 GMT, Fred Bloggs <nospam@nospam.com>
wrote:

John Larkin wrote:
On Wed, 17 Mar 2004 13:02:50 -0700, Jim Thompson
thegreatone@example.com> wrote:

On Wed, 17 Mar 2004 10:05:04 -0800, John Larkin
jjlarkin@highSNIPlandTHIStechPLEASEnology.com> wrote:

[snip]

I have a couple of PLL texts, and none mention bangbang (d-flop) phase
detectors. Does anybody know of books that do?

John

I've only heard of two-D-flop configurations that do edge-matching.
I'm guessing that you mean by "bang-bang" those that put one signal on
"CLK" and one on "D"? That configuration is used more often for
harmonic down conversion (see the Moto PECL parts).

Right. I invented this in about 1972, although I'm sure somebody else
invented it first; my only real claim here is to ignorance.

I did a timing module for the NIF laser that locks a 155.52 MHz vcxo
to an incoming OC3 optical data stream, and used a single EL51
flip-flop as the phase detecor. I had no good ideas as to a proper
math model for the loop, so made some wild guesses and, with a bit of
tweaking, it worked really good... jitter in the 1 ps RMS range, I
think. I had to switch from acquire mode to track mode to make it lock
and have low jitter.

This detector seems to have infinite gain in a noise-free system, and
roughly Vcc/B phase-voltage slope where B is the actual RMS jitter of
the incoming signal. Or something.

Oh, the EL51 has a picosecond or two of setup/hold hysteresis,
depending on the current 1/0 state of the flop.

John

That is probably a third-order loop in reality because you have the very
high-Q VCXO with response time normalized to many oscillation cycles,
maybe hundreds, being updated on a per-cycle basis by the D-FF error
detector. I think the price you pay is one or two orders of magnitude
higher phase noise as compared to a properly linearized loop- because
you are injecting that large amplitude random bit stream into the
control input.

Well, it's hard to beat 1 ps RMS phase noise. The entire module -
optical receiver, PLL, eight 1-ps resolution 3-second range delay
generators, VME interface, 32-bit uP, isolated output drivers - is
running about 3 ps RMS jitter. Good enough.

The reason to not use a linear loop is that I needed extreme absolute
timing accuracy... less than 1/1000 of the incoming 155 MHz clock
period. With a linear detector, tiny DC drifts would swamp this error
budget.

John

Tim Wescott · Mar 19, 2004

"Bill Sloman" <bill.sloman@ieee.org> wrote in message
news:7c584d27.0403171617.21694c7a@posting.google.com...

John Larkin <jjlarkin@highlandSNIPtechTHISnologyPLEASE.com> wrote in
message news:<r7vg50924c6n88hb3qea96vr2jt90app6c@4ax.com>...
On Wed, 17 Mar 2004 16:12:28 GMT, Fred Bloggs <nospam@nospam.com
wrote:

because it means the VCO gain is so high that the only final state
possible is one with zero phase error between the VCO and reference
input.

Zero frequency error, I think.

Floyd M. Gardner's "Phaselock Techniques" (ISBN 0-471-04294-3)
classifies phase-locked loops as first order if they have zero
frequency error but a finite phase error, second order if they have a
zero phase error at static frequency and third order if they track a
varying frequency with zero phase error.

------
Bill Sloman, Nijmegen

I think you're thinking "type 1, 2, etc.", not "order". Control loops are
classified by the number of integrators that they have in the forward part
of the loop -- one integrator gives you zero DC error with a step input, two
gives you zero DC error with a ramp, etc. You can have a 10-gazillionth
order system that still has steady-state error to a step input, which would
make it a type 0 system.

Check any 3rd-year text on control theory.

John Larkin · Mar 19, 2004

On Thu, 18 Mar 2004 11:20:09 GMT, Fred Bloggs <nospam@nospam.com>
wrote:

I always assume the PLL under discussion
is a PLL- frequency reference- ultralow frequency w_sub_n and quadruple
integrated loop filter.

Oh... I don't.

John

Francis · Mar 19, 2004

You mentioned "Thaler and Pastel, Analysis and Design of Nonlinear Feedback
Control Systems"
1962. Looks interesting.

Now it strikes me that that is something that should by now be in the public
domain, ie out of copyright and so freely available. Ideally downloadable.
(Did you know that you can download all of Charles Dickens works ?)

I seached Google for Thaler and Pastel's book and found to my amazement in
'Find a Library' ( www.worldcatlibraries.org) which told me where I could
borrow it from locally. In the UK these are all University libraries.

Just thought you might like to know!

Francis
www.controldraw.com

Help with Laplace Transform for PLL VCO, Kvco?????

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