help in cpu design

[Attila Csosz]

Hi,

I'm working a very-very simple cpu design but it doesnt work. The
problem : the address signal never changed but I dont understand why.

(the file is here)
http://web.axelero.hu/csosz33/cpu_comp.txt

Thanks for any help
Attila

 

[Pieter Hulshoff]

I'm working a very-very simple cpu design but it doesnt work. The
problem : the address signal never changed but I dont understand why.

For starters: the address is set in two different processes. This is asking
for trouble. The same goes for program_counter. Anothing thing I noticed
that no matter what instruction(0 TO 4) is, program_counter is always set
to data in your read_data process.

Regards,

Pieter Hulshoff

 

[Attila Csosz]

Thanks

The main problem : the "read_mem" process of "simple_mem" is never
triggered by "Address". Why? I debugging this with Active-HDL and when I
stepped in the "read_mem" process( triggered by "clk" ) the "Address" is
always "U" but I dont understand why. So "top_A" is "U" during then
simulation.



Pieter Hulshoff wrote:

I'm working a very-very simple cpu design but it doesnt work. The
problem : the address signal never changed but I dont understand why.


For starters: the address is set in two different processes. This is asking

I think this maybe not problem because the "read_instruction" process
read a cpu instruction and if other data need (like jmp) the "read_data"
reads it in and it guarded with "( more_fetch = '1' )".

for trouble. The same goes for program_counter. Anothing thing I noticed
that no matter what instruction(0 TO 4) is, program_counter is always set

ok

to data in your read_data process.

Regards,

Pieter Hulshoff

Thanks for your help
Attila

 

[Pieter Hulshoff]

I think this maybe not problem because the "read_instruction" process
read a cpu instruction and if other data need (like jmp) the "read_data"
reads it in and it guarded with "( more_fetch = '1' )".

I think you may be used to writing software (which is how I started too.
There's no such thing as 'doing nothing' in hardware. Closest you can come
to that is 'keep your current value'. Hence, two processes driving the same
signal will cause trouble unless you're defining a bus with multiple
drivers. As you are not, avoid driving signals from multiple processes, for
if you do your design will not work properly.

Regards,

Pieter

 

[Attila Csosz]

Thanks, I redesign the processes and now the address maybe correct. My
new problem : the top_Ready signal never changes I dont understand why
Maybe like the previous problem but I dont know.. and how to change
to work.

http://web.axelero.hu/csosz33/cpu_comp.txt


Thanks for your help
Attila



Pieter Hulshoff wrote:

I think this maybe not problem because the "read_instruction" process
read a cpu instruction and if other data need (like jmp) the "read_data"
reads it in and it guarded with "( more_fetch = '1' )".


I think you may be used to writing software (which is how I started too.
There's no such thing as 'doing nothing' in hardware. Closest you can come
to that is 'keep your current value'. Hence, two processes driving the same
signal will cause trouble unless you're defining a bus with multiple
drivers. As you are not, avoid driving signals from multiple processes, for
if you do your design will not work properly.

Regards,

Pieter

 

[Pieter Hulshoff]

Thanks, I redesign the processes and now the address maybe correct. My
new problem : the top_Ready signal never changes I dont understand why
Maybe like the previous problem but I dont know.. and how to change
to work.

Well, I personally would use port BUFFER i.s.o. INOUT, but the most likely
reason for your top_Ready not changing is that the Ready output of your
design (to which top_Ready is connected) is driven by two processes. So
yes, it is exactly like the previous problem.

Regards,

Pieter Hulshoff

 

[Attila Csosz]

Ok.. I understand it but then what the role of "resolution function"?

Pieter Hulshoff wrote:

Thanks, I redesign the processes and now the address maybe correct. My
new problem : the top_Ready signal never changes I dont understand why
Maybe like the previous problem but I dont know.. and how to change
to work.


Well, I personally would use port BUFFER i.s.o. INOUT, but the most likely
reason for your top_Ready not changing is that the Ready output of your
design (to which top_Ready is connected) is driven by two processes. So
yes, it is exactly like the previous problem.

Regards,

Pieter Hulshoff

 

[Pieter Hulshoff]

Ok.. I understand it but then what the role of "resolution function"?

It's a function that determines the value of a signal with multiple drivers.
Check out http://www.csee.umbc.edu/help/VHDL/misc.html for the std_ulogic
function to get an idea.

Regards,

Pieter Hulshoff