HELP: Edge triggering of mode register, Verilog

Guest
I'm a relative Verilog noob, and stuck on the following, not sure if
I'm structuring the problem wrongly or if it's just a case of bad
coding. BTW, this is not homework, I'm 40 years too old to be involved
in that caper…

There is a mode register and a man/auto switch. There's also a second
input called Pump. The mode follows the switch, which is trivial, in
addition, on posedge of Pump, the mode has to transition to auto.
Hence, edge triggering is required.

The applicable Verilog code is like this:

input Switch ; // man/auto switch
input Pump ;
reg Mode ;

always @ (posedge Switch) Mode <= 1 ;
always @ (negedge Switch) Mode <= 0 ;
always @ (posedge Pump) Mode <= 1 ;

Here are the build errors (Quartus II)

Error (10028): Can't resolve multiple constant drivers for net "Mode"
at OWPump4.v(62)
Error (10029): Constant driver at OWPump4.v(61)

Any assistance really appreciated.
 
On 6/8/2014 12:08 AM, Bruce Varley wrote:
I'm a relative Verilog noob, and stuck on the following, not sure if
I'm structuring the problem wrongly or if it's just a case of bad
coding. BTW, this is not homework, I'm 40 years too old to be involved
in that caper…

There is a mode register and a man/auto switch. There's also a second
input called Pump. The mode follows the switch, which is trivial, in
addition, on posedge of Pump, the mode has to transition to auto.
Hence, edge triggering is required.

The applicable Verilog code is like this:

input Switch ; // man/auto switch
input Pump ;
reg Mode ;

always @ (posedge Switch) Mode <= 1 ;
always @ (negedge Switch) Mode <= 0 ;
always @ (posedge Pump) Mode <= 1 ;

Here are the build errors (Quartus II)

Error (10028): Can't resolve multiple constant drivers for net "Mode"
at OWPump4.v(62)
Error (10029): Constant driver at OWPump4.v(61)

Any assistance really appreciated.
Click to expand...

I'm no expert in Verilog, I'm much more a VHDL guy. When I need to work
in it I have to pull out the books to refresh my memory of the syntax,
etc or I just pull up my previous code and review it. But I can see
what you are doing wrong easily.

Mode is a single variable which can only be assigned in one process...
(remember that I'm a VHDL guy so maybe this is wrong). You seem to have
three processes. The edge thing is for when you are defining a clocked
register, you refer to the edge of the clock. So it would be more like...

always @ (posedge clock)
if (Switch = 1) then
Mode <= 1;
else
Mode <= Pump;
end if;

I know this is not the correct syntax. Verilog is similar to C and uses
those curly braces in if statements and to define blocks of code.
Consider this to be pseudo code.

Do a little searching on the Internet and see what sort of text book or
lectures you can find. I know there is lots of good material on writing
VHDL. Also, it might help if you consider what the circuit would look
like in hardware and then learn how to describe that hardware in the HDL.

One other thing. For the above design you don't really need a register.
The man/auto switch acts as your memory element. You just need the
logic.

Mode <= Switch or Pump;

I hope this helps some. Sorry I couldn't be more sure of myself. Maybe
tomorrow I'll pull out a book and get the exact syntax.

--

Rick
 
Bruce wrote:
I'm a relative Verilog noob, and stuck on the following, not sure if
I'm structuring the problem wrongly or if it's just a case of bad
coding. BTW, this is not homework, I'm 40 years too old to be involved
in that caper?

There is a mode register and a man/auto switch. There's also a second
input called Pump. The mode follows the switch, which is trivial, in
addition, on posedge of Pump, the mode has to transition to auto.
Hence, edge triggering is required.

The applicable Verilog code is like this:

input Switch ; // man/auto switch
input Pump ;
reg Mode ;

always @ (posedge Switch) Mode <= 1 ;
always @ (negedge Switch) Mode <= 0 ;
always @ (posedge Pump) Mode <= 1 ;
Click to expand...

edge triggered registers should look like

always @(posedge clock) q <= d;

d can be a complicated (combinatorial) expression.

I like to put registers inside a module, just the register,
then invoke that module, but you don't have to do that.

You should only have one always @ assigning to the register output.

-- glen
 
Hi,

your approach is typical digital-design textbook but it's completely wron
for an FPGA, sorry.
It will work for a small example but it doesn't scale.

On FPGAs, use synchronous logic. That means, information and the timing i
separated. You have information signals and clocks. Edge triggering is don
on clocks only.
This matters because clock and information signals are physically separat
on the FPGA and you cannot use one in place of the other.

The problem is, generic Verilog tutorials, books etc aren't necessaril
applicable to FPGA, because the language is more capable than the hardware
The same for digital design, the FPGA hardware dictates what you can do an
(mostly) how it should be done.

Here's how it should look instead: The task is to act on opening or closin
switches - detect a transition of the switch signal.
I use a "clk" signal that is available on every FPGA board, let's' say 10
MHz (or whatever)

input wire switch;
reg switch_prev = 0;
wire switchOn = (switch & !switchPrev);
wire switchOff = (!switch && switchPrev);
reg pump = 0;

always @(posedge clk) begin
if (switchOn) begin pump <= 1; end
if (switchOff) begin pump <= 0; end
end


You could read up on "Moore" (and "Mealy") machines as a starting point fo
synchronous logic design. Once I manage to formulate the task as Moor
machine, an FPGA implementation is only a formality.
It may seem abstract at first, but it's a straightforward path through th
digital design "jungle".

---------------------------------------
Posted through http://www.FPGARelated.com
 
On Sun, 08 Jun 2014 06:15:03 -0500, "mnentwig" <24789@embeddedrelated>
wrote:

Hi,

your approach is typical digital-design textbook but it's completely wrong
for an FPGA, sorry.
It will work for a small example but it doesn't scale.

On FPGAs, use synchronous logic. That means, information and the timing is
separated. You have information signals and clocks. Edge triggering is done
on clocks only.
This matters because clock and information signals are physically separate
on the FPGA and you cannot use one in place of the other.

The problem is, generic Verilog tutorials, books etc aren't necessarily
applicable to FPGA, because the language is more capable than the hardware.
The same for digital design, the FPGA hardware dictates what you can do and
(mostly) how it should be done.

Here's how it should look instead: The task is to act on opening or closing
switches - detect a transition of the switch signal.
I use a "clk" signal that is available on every FPGA board, let's' say 100
MHz (or whatever)

input wire switch;
reg switch_prev = 0;
wire switchOn = (switch & !switchPrev);
wire switchOff = (!switch && switchPrev);
reg pump = 0;

always @(posedge clk) begin
if (switchOn) begin pump <= 1; end
if (switchOff) begin pump <= 0; end
end


You could read up on "Moore" (and "Mealy") machines as a starting point for
synchronous logic design. Once I manage to formulate the task as Moore
machine, an FPGA implementation is only a formality.
It may seem abstract at first, but it's a straightforward path through the
digital design "jungle".

---------------------------------------
Posted through http://www.FPGARelated.com

#define MAXSUBST 40
Click to expand...
Thanks very much, guys,. Your explanations have helped me understand
the situation much better.
 
Hi,

one line was missing:

input wire switch;
reg switchPrev = 0;
wire switchOn = (switch & !switchPrev);
wire switchOff = (!switch && switchPrev);
reg pump = 0;

always @(posedge clk) begin
switchPrev <= switch;
if (switchOn) begin pump <= 1; end
if (switchOff) begin pump <= 0; end
end

What's important to know is that "<=" assignments only becomes effectiv
after the ongoing clock cycle has completed. The wire "=" assignments i
this example are combinational logic and cause zero delay.


---------------------------------------
Posted through http://www.FPGARelated.com
 
On Sun, 08 Jun 2014 08:21:19 -0500, "mnentwig" <24789@embeddedrelated>
wrote:

Hi,

one line was missing:

input wire switch;
reg switchPrev = 0;
wire switchOn = (switch & !switchPrev);
wire switchOff = (!switch && switchPrev);
reg pump = 0;

always @(posedge clk) begin
switchPrev <= switch;
if (switchOn) begin pump <= 1; end
if (switchOff) begin pump <= 0; end
end

What's important to know is that "<=" assignments only becomes effective
after the ongoing clock cycle has completed. The wire "=" assignments in
this example are combinational logic and cause zero delay.


---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...

Thanks. I'm designing it as a state machine (I use them already for
industrial sequencing applications). This is a good illustration of
how the state model sometimes has a shape that differs from what you
think it might be. Cheers
 
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