Guest
I'm a relative Verilog noob, and stuck on the following, not sure if
I'm structuring the problem wrongly or if it's just a case of bad
coding. BTW, this is not homework, I'm 40 years too old to be involved
in that caper
There is a mode register and a man/auto switch. There's also a second
input called Pump. The mode follows the switch, which is trivial, in
addition, on posedge of Pump, the mode has to transition to auto.
Hence, edge triggering is required.
The applicable Verilog code is like this:
input Switch ; // man/auto switch
input Pump ;
reg Mode ;
always @ (posedge Switch) Mode <= 1 ;
always @ (negedge Switch) Mode <= 0 ;
always @ (posedge Pump) Mode <= 1 ;
Here are the build errors (Quartus II)
Error (10028): Can't resolve multiple constant drivers for net "Mode"
at OWPump4.v(62)
Error (10029): Constant driver at OWPump4.v(61)
Any assistance really appreciated.
I'm structuring the problem wrongly or if it's just a case of bad
coding. BTW, this is not homework, I'm 40 years too old to be involved
in that caper
There is a mode register and a man/auto switch. There's also a second
input called Pump. The mode follows the switch, which is trivial, in
addition, on posedge of Pump, the mode has to transition to auto.
Hence, edge triggering is required.
The applicable Verilog code is like this:
input Switch ; // man/auto switch
input Pump ;
reg Mode ;
always @ (posedge Switch) Mode <= 1 ;
always @ (negedge Switch) Mode <= 0 ;
always @ (posedge Pump) Mode <= 1 ;
Here are the build errors (Quartus II)
Error (10028): Can't resolve multiple constant drivers for net "Mode"
at OWPump4.v(62)
Error (10029): Constant driver at OWPump4.v(61)
Any assistance really appreciated.