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How does schematic work?
To be frank - I've got no idea. But the flow presented by the software seem different.
Tried and re-licenced the software - the licence.dat contains all the packages, including Syn stuff. So this shouldn't (at least theoretically) be the cause.
If the tool has a button for firing up the simulator without doing a
compile (the Diamond and iCE40 tools do) see if you can bring up the
GUI. If you can, the license is good.
On Thursday, 16 June 2016 23:48:07 UTC+2, silverdr wrote:
On Thursday, 16 June 2016 19:06:04 UTC+2, rickman wrote:
I don't know for sure, but Synplicity should need a license to run. I
seem to recall when my license expires I get an exit error of 2. Check
the Lattice web site to see what they say about licensing this tool.
I'll have a look anyway.
Tried and re-licenced the software - the licence.dat contains all the packages, including Syn stuff. So this shouldn't (at least theoretically) be the cause.
On Monday, 20 June 2016 19:14:27 UTC+2, rickman wrote:
Tried and re-licenced the software - the licence.dat contains all the packages, including Syn stuff. So this shouldn't (at least theoretically) be the cause.
If the tool has a button for firing up the simulator without doing a
compile (the Diamond and iCE40 tools do) see if you can bring up the
GUI. If you can, the license is good.
The closest I can think of are the menu entries named "Waveform editor" and "Waveform viewer". Both pop up normally.
Hello group (and please have understanding for a newbie in the subject).
I'd like to make use of GAL chips for a relatively simple logic I need to build. Nine inputs to five outputs, purely combinatorial, non-clocked. I wrote VHDL design and testbench and successfully tested it on edaplayground.com. Now, I'd like to synthesise it and then comes some questions:
- what software (preferably but not necessarily free as in speech and open-source) should I use for that? I have 16V8 and 20V8 chips from Lattice, Atmel and one or two more vendors (don't remember exactly now).
- are the synthesised files compatible across different vendors' chips?
- If there is a GAL (16V8 for example) which has eight inputs and eight Output Logic MacroCells, can some of those OLMCs/pins be configured and used as inputs too? Judging by the specs/datasheet "yes" but would like to confirm that.
So far I downloaded and installed the ispLEVER from Lattice, which is still available and supports "obsolete" devices like GALs. The problem is that when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I get output like:
*******
Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro '
Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved.
Version : 2.0.00.17.20.15
Done sucessfully with exit code 1.
Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2
Done: failed with exit code: 0002.
*******
and am stuck at it.
I know there is a CUPL software available from Atmel, and it should be able to synthesise designs for GALs but I would prefer to stick to VHDL, which I assume is going to stay with me for some time to come. Therefore rewriting the design into CUPL is probably the last resort.
I'd be grateful for some clues/hints/pointers.
--
silverdr
On Wednesday, June 15, 2016 at 9:41:35 AM UTC-6, silverdr wrote:
So far I downloaded and installed the ispLEVER from Lattice, which is
still available and supports "obsolete" devices like GALs. The problem
is that when I try to do some synthesis using
ispLEVER/PureVHDL/Synplify/ project I get output like:
*******
Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl
-target ispGAL -pro '
Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights
reserved.
Version : 2.0.00.17.20.15
Done sucessfully with exit code 1.
Error output EDIF file c:/documents and settings/silverdr/my
documents/sources/vhdl/r512/r512vhdl.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2
Done: failed with exit code: 0002.
*******
I have the same problem... when I do Synthesize there appears the next error:
Error output EDIF file c:/isplever_classic2_0/examples/ESumRes.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2
...
How did you fix it?