S
silverdr
Guest
Hello group (and please have understanding for a newbie in the subject).
I'd like to make use of GAL chips for a relatively simple logic I need to build. Nine inputs to five outputs, purely combinatorial, non-clocked. I wrote VHDL design and testbench and successfully tested it on edaplayground.com. Now, I'd like to synthesise it and then comes some questions:
- what software (preferably but not necessarily free as in speech and open-source) should I use for that? I have 16V8 and 20V8 chips from Lattice, Atmel and one or two more vendors (don't remember exactly now).
- are the synthesised files compatible across different vendors' chips?
- If there is a GAL (16V8 for example) which has eight inputs and eight Output Logic MacroCells, can some of those OLMCs/pins be configured and used as inputs too? Judging by the specs/datasheet "yes" but would like to confirm that.
So far I downloaded and installed the ispLEVER from Lattice, which is still available and supports "obsolete" devices like GALs. The problem is that when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I get output like:
*******
Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro '
Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved.
Version : 2.0.00.17.20.15
Done sucessfully with exit code 1.
Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2
Done: failed with exit code: 0002.
*******
and am stuck at it.
I know there is a CUPL software available from Atmel, and it should be able to synthesise designs for GALs but I would prefer to stick to VHDL, which I assume is going to stay with me for some time to come. Therefore rewriting the design into CUPL is probably the last resort.
I'd be grateful for some clues/hints/pointers.
--
silverdr
I'd like to make use of GAL chips for a relatively simple logic I need to build. Nine inputs to five outputs, purely combinatorial, non-clocked. I wrote VHDL design and testbench and successfully tested it on edaplayground.com. Now, I'd like to synthesise it and then comes some questions:
- what software (preferably but not necessarily free as in speech and open-source) should I use for that? I have 16V8 and 20V8 chips from Lattice, Atmel and one or two more vendors (don't remember exactly now).
- are the synthesised files compatible across different vendors' chips?
- If there is a GAL (16V8 for example) which has eight inputs and eight Output Logic MacroCells, can some of those OLMCs/pins be configured and used as inputs too? Judging by the specs/datasheet "yes" but would like to confirm that.
So far I downloaded and installed the ispLEVER from Lattice, which is still available and supports "obsolete" devices like GALs. The problem is that when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I get output like:
*******
Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro '
Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved.
Version : 2.0.00.17.20.15
Done sucessfully with exit code 1.
Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2
Done: failed with exit code: 0002.
*******
and am stuck at it.
I know there is a CUPL software available from Atmel, and it should be able to synthesise designs for GALs but I would prefer to stick to VHDL, which I assume is going to stay with me for some time to come. Therefore rewriting the design into CUPL is probably the last resort.
I'd be grateful for some clues/hints/pointers.
--
silverdr