FPGA < -- > Processor timing Violations

P

Pravin

Guest
Hi,

I'm interfacing Actel FPGA with Freescale Coldfire Processor. This
interface is operating @ 75Mhz.
FPGA output signal (TA -Transfer acknowledge) and FPGA data out is
sampled at rising edge by Processor.

As per Coldfire Processor datasheet, setup time for this signals is
9ns and 0ns is hold time.

I am giving constraints as follows.

#Period constraint
create_clock -name { i_PROC_CLKOUT } -period 13.333 -waveform { 0.000
6.667 } { i_PROC_CLKOUT }

set_input_delay 11.667 -clock { i_PROC_CLKOUT } [get_ports
{ i_PROC_CS1n }]

# adding 1ns to account PCB trace delay
set_output_delay 10.000 -clock { i_PROC_CLKOUT } [get_ports
{ o_PROC_TAn }]

Here if I just delay my input signal and connected to output pin, my
timings are not met (slack is -4.745ns).

How do operate the design (glue logic) at 75MHz without any timing
violations?

always @(posedge i_PROC_CLKOUT or negedge i_RESETn)
begin
if(i_RESETn == 1'b0)
r_sync_proc_cs1n &lt;= 1'b1;
else
r_sync_proc_cs1n &lt;= i_PROC_CS1n ;
end
assign o_PROC_TAn = r_sync_proc_cs1n;

Thanks in advance.
 
On Jul 26, 2:40 am, Pravin &lt;gavatepra...@gmail.com&gt; wrote:
Hi,

I'm interfacing Actel FPGA with Freescale Coldfire Processor. This
interface is operating @ 75Mhz.
FPGA output signal (TA -Transfer acknowledge) and FPGA data out is
sampled at rising edge by Processor.

As per Coldfire Processor datasheet, setup time for this signals is
9ns and 0ns is hold time.

I am giving constraints as follows.

#Period constraint
create_clock  -name { i_PROC_CLKOUT } -period 13.333 -waveform { 0.000
6.667  }  { i_PROC_CLKOUT  }

set_input_delay 11.667 -clock { i_PROC_CLKOUT }  [get_ports
{ i_PROC_CS1n }]

# adding 1ns to account PCB trace delay
set_output_delay 10.000 -clock { i_PROC_CLKOUT }  [get_ports
{ o_PROC_TAn }]

Here if I just delay my input signal and connected to output pin, my
timings are not met (slack is -4.745ns).

How do operate the design (glue logic) at 75MHz without any timing
violations?

always @(posedge i_PROC_CLKOUT or negedge i_RESETn)
begin
  if(i_RESETn == 1'b0)
        r_sync_proc_cs1n        &lt;= 1'b1;
  else
        r_sync_proc_cs1n        &lt;= i_PROC_CS1n ;
end
assign o_PROC_TAn = r_sync_proc_cs1n;

Thanks in advance.
Click to expand...
Not familiar with Actel FPGAs. But if they are like Altera or Xilinxs,
then they have a register in the i/o block. You could check to see if
the r_sync_proc_cs1n is placed in the iob. Ofcourse, I am assuming
that you can easily achive tco of &lt; 3.33ns if you locate a register in
the iob and the clock is on a high-speed route.

You can also try to clock the register on the opposite edge of the
clock or register both input and output.
 
On Jul 26, 10:35 pm, fpgabuilder &lt;parekh...@gmail.com&gt; wrote:
On Jul 26, 2:40 am, Pravin &lt;gavatepra...@gmail.com&gt; wrote:



Hi,

I'm interfacing Actel FPGA with Freescale Coldfire Processor. This
interface is operating @ 75Mhz.
FPGA output signal (TA -Transfer acknowledge) and FPGA data out is
sampled at rising edge by Processor.

As per Coldfire Processor datasheet, setup time for this signals is
9ns and 0ns is hold time.

I am giving constraints as follows.

#Period constraint
create_clock  -name { i_PROC_CLKOUT } -period 13.333 -waveform { 0.000
6.667  }  { i_PROC_CLKOUT  }

set_input_delay 11.667 -clock { i_PROC_CLKOUT }  [get_ports
{ i_PROC_CS1n }]

# adding 1ns to account PCB trace delay
set_output_delay 10.000 -clock { i_PROC_CLKOUT }  [get_ports
{ o_PROC_TAn }]

Here if I just delay my input signal and connected to output pin, my
timings are not met (slack is -4.745ns).

How do operate the design (glue logic) at 75MHz without any timing
violations?

always @(posedge i_PROC_CLKOUT or negedge i_RESETn)
begin
  if(i_RESETn == 1'b0)
        r_sync_proc_cs1n        &lt;= 1'b1;
  else
        r_sync_proc_cs1n        &lt;= i_PROC_CS1n ;
end
assign o_PROC_TAn = r_sync_proc_cs1n;

Thanks in advance.

Not familiar with Actel FPGAs. But if they are like Altera or Xilinxs,
then they have a register in the i/o block.  You could check to see if
the r_sync_proc_cs1n is placed in the iob.  Ofcourse, I am assuming
that you can easily achive tco of &lt; 3.33ns if you locate a register in
the iob and the clock is on a high-speed route.

You can also try to clock the register on the opposite edge of the
clock or register both input and output.
Click to expand...
Hi,
Here, this register is packed in IOB register and clock is routed with
global clock line.
But clock to output is coming 5.906ns. Even I tried to increase the
drive strength, it is slightly reduced (5.705ns) and not meeting tco -
3.33ns.

If I try to put this register on another edge, then 10ns output delay
is not meeting.

Can anyone suggest me another method to work the design using above
constraints.

I am thinking to delay the Transfer Acknowledge and data output
signals using BUFD macro such that setup and hold time of processor
met. Is this correct way to do this.

Thanks,
Pravin
 
On 2010-07-27, Pravin &lt;gavatepravin@gmail.com&gt; wrote:
But clock to output is coming 5.906ns. Even I tried to increase the
drive strength, it is slightly reduced (5.705ns) and not meeting tco -
3.33ns.
Click to expand...
I'm by no means an FPGA I/O expert, but have you considered using a
DLL or PLL in the FPGA to manage your internal clock phase?

regards
/Andreas
 
On Jul 28, 1:36 pm, Andreas Ehliar &lt;ehliar-nos...@isy.liu.se&gt; wrote:
On 2010-07-27, Pravin &lt;gavatepra...@gmail.com&gt; wrote:

But clock to output is coming 5.906ns. Even I tried to increase the
drive strength, it is slightly reduced (5.705ns) and not meeting tco -
3.33ns.

I'm by no means an FPGA I/O expert, but have you considered using a
DLL or PLL in the FPGA to manage your internal clock phase?

regards
/Andreas

have you considered using a DLL or PLL in the FPGA to manage your internal clock phase?
Click to expand...
I am new for this. Can you please elaborate this in more detail to
solve this timing problem?

Thanks,
Pravin
 
On 2010-07-28, Pravin &lt;gavatepravin@gmail.com&gt; wrote:
I am new for this. Can you please elaborate this in more detail to
solve this timing problem?
Click to expand...
The DLL can basically make sure that the delay of internal clock
distribution network is eliminated [1]. XAPP174 from Xilinx has a
nice introduction to the delay-locked loop on page 2 together with
an introduction to a phase-locked loop [2]. However, I have never
used an Actel device, so I can't give you any hints on exactly how
the clock manager in actel works.

regards
/Andreas

[1] It does this by delaying the incoming clock until it is delayed
so much that the internal clock edges coincide with the incoming
clock edges.
[2] http://www.xilinx.com/support/documentation/application_notes/xapp174.pdf
 
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