V
Victor Salazar
Guest
when i try to compile thisin ModelSim..
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY Lab_2 IS
PORT
(
ina1 : IN STD_LOGIC;
ina2 : IN STD_LOGIC;
ina3 : IN STD_LOGIC;
ina4 : IN STD_LOGIC;
inb1 : IN STD_LOGIC;
inb2 : IN STD_LOGIC;
inb3 : IN STD_LOGIC;
inb4 : IN STD_LOGIC;
o1 : OUT STD_LOGIC;
o2 : OUT STD_LOGIC;
o3 : OUT STD_LOGIC;
o4 : OUT STD_LOGIC;
outacarreo : OUT STD_LOGIC
);
END Lab_2;
ARCHITECTURE bdf_type OF Lab_2 IS
--ATTRIBUTE black_box : BOOLEAN;
--ATTRIBUTE noopt : BOOLEAN;
COMPONENT 7483
PORT(C0 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
S3 : OUT STD_LOGIC;
S4 : OUT STD_LOGIC;
S2 : OUT STD_LOGIC;
C4 : OUT STD_LOGIC;
S1 : OUT STD_LOGIC)
END COMPONENT;
--ATTRIBUTE black_box OF 7483 : COMPONENT IS true;
--ATTRIBUTE noopt OF 7483 : COMPONENT IS true;
SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC;
SIGNAL o11 : STD_LOGIC;
SIGNAL o12 : STD_LOGIC;
SIGNAL o13 : STD_LOGIC;
SIGNAL o14 : STD_LOGIC;
BEGIN
SYNTHESIZED_WIRE_16 <= \'0\';
b2v_inst : 7483
PORT MAP(B4 => inb4,
A1 => ina1,
A2 => ina2,
B1 => inb1,
B2 => inb2,
A3 => ina3,
B3 => inb3,
A4 => ina4,
S3 => SYNTHESIZED_WIRE_19,
S4 => SYNTHESIZED_WIRE_20,
S2 => SYNTHESIZED_WIRE_17,
C4 => SYNTHESIZED_WIRE_12,
S1 => SYNTHESIZED_WIRE_1);
b2v_inst1 : 7483
PORT MAP(B4 => SYNTHESIZED_WIRE_16,
A1 => SYNTHESIZED_WIRE_1,
A2 => SYNTHESIZED_WIRE_17,
B1 => SYNTHESIZED_WIRE_16,
B2 => SYNTHESIZED_WIRE_18,
A3 => SYNTHESIZED_WIRE_19,
B3 => SYNTHESIZED_WIRE_18,
A4 => SYNTHESIZED_WIRE_20,
S3 => o13,
S4 => o14,
S2 => o12,
C4 => SYNTHESIZED_WIRE_15,
S1 => o11);
SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_8 AND SYNTHESIZED_WIRE_20;
SYNTHESIZED_WIRE_8 <= SYNTHESIZED_WIRE_19 OR SYNTHESIZED_WIRE_17;
SYNTHESIZED_WIRE_18 <= SYNTHESIZED_WIRE_12 OR SYNTHESIZED_WIRE_13;
outacarreo <= SYNTHESIZED_WIRE_18 OR SYNTHESIZED_WIRE_15;
o1 <= o11;
o2 <= o12;
o3 <= o13;
o4 <= o14;
END bdf_type;
it gives me this error...
** Error: D:/MECATRONICA/7mo semestre/Hardware rec/tareas 2do parcial/quartus 2/lab 3/Lab 2.vhd(50): near \"7483\": expecting IDENTIFIER
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
LIBRARY work;
ENTITY Lab_2 IS
PORT
(
ina1 : IN STD_LOGIC;
ina2 : IN STD_LOGIC;
ina3 : IN STD_LOGIC;
ina4 : IN STD_LOGIC;
inb1 : IN STD_LOGIC;
inb2 : IN STD_LOGIC;
inb3 : IN STD_LOGIC;
inb4 : IN STD_LOGIC;
o1 : OUT STD_LOGIC;
o2 : OUT STD_LOGIC;
o3 : OUT STD_LOGIC;
o4 : OUT STD_LOGIC;
outacarreo : OUT STD_LOGIC
);
END Lab_2;
ARCHITECTURE bdf_type OF Lab_2 IS
--ATTRIBUTE black_box : BOOLEAN;
--ATTRIBUTE noopt : BOOLEAN;
COMPONENT 7483
PORT(C0 : IN STD_LOGIC;
B4 : IN STD_LOGIC;
A1 : IN STD_LOGIC;
A2 : IN STD_LOGIC;
B1 : IN STD_LOGIC;
B2 : IN STD_LOGIC;
A3 : IN STD_LOGIC;
B3 : IN STD_LOGIC;
A4 : IN STD_LOGIC;
S3 : OUT STD_LOGIC;
S4 : OUT STD_LOGIC;
S2 : OUT STD_LOGIC;
C4 : OUT STD_LOGIC;
S1 : OUT STD_LOGIC)
END COMPONENT;
--ATTRIBUTE black_box OF 7483 : COMPONENT IS true;
--ATTRIBUTE noopt OF 7483 : COMPONENT IS true;
SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_17 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_8 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_12 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;
SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC;
SIGNAL o11 : STD_LOGIC;
SIGNAL o12 : STD_LOGIC;
SIGNAL o13 : STD_LOGIC;
SIGNAL o14 : STD_LOGIC;
BEGIN
SYNTHESIZED_WIRE_16 <= \'0\';
b2v_inst : 7483
PORT MAP(B4 => inb4,
A1 => ina1,
A2 => ina2,
B1 => inb1,
B2 => inb2,
A3 => ina3,
B3 => inb3,
A4 => ina4,
S3 => SYNTHESIZED_WIRE_19,
S4 => SYNTHESIZED_WIRE_20,
S2 => SYNTHESIZED_WIRE_17,
C4 => SYNTHESIZED_WIRE_12,
S1 => SYNTHESIZED_WIRE_1);
b2v_inst1 : 7483
PORT MAP(B4 => SYNTHESIZED_WIRE_16,
A1 => SYNTHESIZED_WIRE_1,
A2 => SYNTHESIZED_WIRE_17,
B1 => SYNTHESIZED_WIRE_16,
B2 => SYNTHESIZED_WIRE_18,
A3 => SYNTHESIZED_WIRE_19,
B3 => SYNTHESIZED_WIRE_18,
A4 => SYNTHESIZED_WIRE_20,
S3 => o13,
S4 => o14,
S2 => o12,
C4 => SYNTHESIZED_WIRE_15,
S1 => o11);
SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_8 AND SYNTHESIZED_WIRE_20;
SYNTHESIZED_WIRE_8 <= SYNTHESIZED_WIRE_19 OR SYNTHESIZED_WIRE_17;
SYNTHESIZED_WIRE_18 <= SYNTHESIZED_WIRE_12 OR SYNTHESIZED_WIRE_13;
outacarreo <= SYNTHESIZED_WIRE_18 OR SYNTHESIZED_WIRE_15;
o1 <= o11;
o2 <= o12;
o3 <= o13;
o4 <= o14;
END bdf_type;
it gives me this error...
** Error: D:/MECATRONICA/7mo semestre/Hardware rec/tareas 2do parcial/quartus 2/lab 3/Lab 2.vhd(50): near \"7483\": expecting IDENTIFIER