Driver to drive?

Jim Thompson · Mar 8, 2012

On Tue, 06 Mar 2012 21:54:41 -0800, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Tue, 06 Mar 2012 19:30:48 -0600, John Fields
jfields@austininstruments.com> wrote:

[snip]
---
Ah, but there's yet more to come, illustrating how the lot of you who
can't make decisions between clock transitions are crippled.

Synchronous logic makes decisions between clocks, namely executes the
combinational logic that maps the current system state into the next
one. But it doesn't *act* on those decisions until they are stable,
and then only at the next clock. It's not the only way to design
logic, but it's the only practical way to design reliable logic of any
complexity, as your circuit bugs demonstrate.

Wikipedia has an article on async logic, and includes a long list of
async computer designs that never made it to production. Intel among
others has dabbled in async design and there are rumors that some
sections of some of their CPUs are async logic. Also rumors that an
async x86 design was scrapped in 1997.

Stay tuned...

Can't wait.

I'm certainly no logician, but surfing on "async logic" brings up some
interesting discussion that async can result in 40% power savings, but
takes more gates to do so. Considering the continual reduction in
ASIC feature size, considerable effort is in play for using async in
portable devices and in medical implants. The biggest impediment
right now to that development is the lack of async synthesis tools.

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice

John Larkin · Mar 8, 2012

On Thu, 08 Mar 2012 08:53:14 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Tue, 06 Mar 2012 21:54:41 -0800, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Tue, 06 Mar 2012 19:30:48 -0600, John Fields
jfields@austininstruments.com> wrote:

[snip]
---
Ah, but there's yet more to come, illustrating how the lot of you who
can't make decisions between clock transitions are crippled.

Synchronous logic makes decisions between clocks, namely executes the
combinational logic that maps the current system state into the next
one. But it doesn't *act* on those decisions until they are stable,
and then only at the next clock. It's not the only way to design
logic, but it's the only practical way to design reliable logic of any
complexity, as your circuit bugs demonstrate.

Wikipedia has an article on async logic, and includes a long list of
async computer designs that never made it to production. Intel among
others has dabbled in async design and there are rumors that some
sections of some of their CPUs are async logic. Also rumors that an
async x86 design was scrapped in 1997.

Stay tuned...

Can't wait.

I'm certainly no logician, but surfing on "async logic" brings up some
interesting discussion that async can result in 40% power savings, but
takes more gates to do so. Considering the continual reduction in
ASIC feature size, considerable effort is in play for using async in
portable devices and in medical implants. The biggest impediment
right now to that development is the lack of async synthesis tools.

...Jim Thompson

That's been the problem for decades. Synchronous logic synthesis and
analysis separates the issue of logic correctness (pure state machine
stuff) from the issue of timing analysis, namely how fast can you
clock it reliably. Pipelining is a major tool to fix the problem of
the combinational logic limiting clock rates, but pipelined logic is
still just logic.

Async logic tangles the logic functionality with the speed issues. I'd
imagine that the simulation burden explodes when you do async logic:
what had been logical simulation becomes essentially analog
simulation. Imagine simulating an analog circuit that has a billion
transistors and thousands of inputs and outputs. Now do that over Vcc
and process variations and temperature.

--

John Larkin, President Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

Jim Thompson · Mar 8, 2012

On Thu, 08 Mar 2012 08:38:49 -0800, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Thu, 08 Mar 2012 08:53:14 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Tue, 06 Mar 2012 21:54:41 -0800, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Tue, 06 Mar 2012 19:30:48 -0600, John Fields
jfields@austininstruments.com> wrote:

[snip]
---
Ah, but there's yet more to come, illustrating how the lot of you who
can't make decisions between clock transitions are crippled.

Synchronous logic makes decisions between clocks, namely executes the
combinational logic that maps the current system state into the next
one. But it doesn't *act* on those decisions until they are stable,
and then only at the next clock. It's not the only way to design
logic, but it's the only practical way to design reliable logic of any
complexity, as your circuit bugs demonstrate.

Wikipedia has an article on async logic, and includes a long list of
async computer designs that never made it to production. Intel among
others has dabbled in async design and there are rumors that some
sections of some of their CPUs are async logic. Also rumors that an
async x86 design was scrapped in 1997.

Stay tuned...

Can't wait.

I'm certainly no logician, but surfing on "async logic" brings up some
interesting discussion that async can result in 40% power savings, but
takes more gates to do so. Considering the continual reduction in
ASIC feature size, considerable effort is in play for using async in
portable devices and in medical implants. The biggest impediment
right now to that development is the lack of async synthesis tools.

...Jim Thompson

That's been the problem for decades. Synchronous logic synthesis and
analysis separates the issue of logic correctness (pure state machine
stuff) from the issue of timing analysis, namely how fast can you
clock it reliably. Pipelining is a major tool to fix the problem of
the combinational logic limiting clock rates, but pipelined logic is
still just logic.

Async logic tangles the logic functionality with the speed issues. I'd
imagine that the simulation burden explodes when you do async logic:
what had been logical simulation becomes essentially analog
simulation.

Not so. Logic simulation remains logic simulation. Take the student
version of PSpice for a test drive and see how the logic simulator
works... it'll spit out all the hazards in a nice list.

I would imagine, at least for analysis, that VHDL and Verilog will
continue to work. Synthesis is the difficulty.

Imagine simulating an analog circuit that has a billion
transistors and thousands of inputs and outputs. Now do that over Vcc
and process variations and temperature.

John Larkin · Mar 8, 2012

On Thu, 08 Mar 2012 09:50:25 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Thu, 08 Mar 2012 08:38:49 -0800, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Thu, 08 Mar 2012 08:53:14 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Tue, 06 Mar 2012 21:54:41 -0800, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Tue, 06 Mar 2012 19:30:48 -0600, John Fields
jfields@austininstruments.com> wrote:

[snip]
---
Ah, but there's yet more to come, illustrating how the lot of you who
can't make decisions between clock transitions are crippled.

Synchronous logic makes decisions between clocks, namely executes the
combinational logic that maps the current system state into the next
one. But it doesn't *act* on those decisions until they are stable,
and then only at the next clock. It's not the only way to design
logic, but it's the only practical way to design reliable logic of any
complexity, as your circuit bugs demonstrate.

Wikipedia has an article on async logic, and includes a long list of
async computer designs that never made it to production. Intel among
others has dabbled in async design and there are rumors that some
sections of some of their CPUs are async logic. Also rumors that an
async x86 design was scrapped in 1997.

Stay tuned...

Can't wait.

I'm certainly no logician, but surfing on "async logic" brings up some
interesting discussion that async can result in 40% power savings, but
takes more gates to do so. Considering the continual reduction in
ASIC feature size, considerable effort is in play for using async in
portable devices and in medical implants. The biggest impediment
right now to that development is the lack of async synthesis tools.

...Jim Thompson

That's been the problem for decades. Synchronous logic synthesis and
analysis separates the issue of logic correctness (pure state machine
stuff) from the issue of timing analysis, namely how fast can you
clock it reliably. Pipelining is a major tool to fix the problem of
the combinational logic limiting clock rates, but pipelined logic is
still just logic.

Async logic tangles the logic functionality with the speed issues. I'd
imagine that the simulation burden explodes when you do async logic:
what had been logical simulation becomes essentially analog
simulation.

Not so. Logic simulation remains logic simulation. Take the student
version of PSpice for a test drive and see how the logic simulator
works... it'll spit out all the hazards in a nice list.

I would imagine, at least for analysis, that VHDL and Verilog will
continue to work. Synthesis is the difficulty.

VHDL is not an analysis language, it's a logic description language.
Actual gates and flops are synthesized downstream, with other tools,
and may look very different from the VHDL when it's actually mapped
into specific hardware.

There are VHDL simulation programs, but they usually work from the
VHDL itself, not the synthesized logic. What we usually do is sim at
VHDL level and do static timing analysis (which is ignorant of the
logic intent) after logic synthesis, and hope that the logic synthesis
stuff worked.

One could write an async logic design in VHDL - just don't clock
anything - but I don't know where you'd go from that, or how you'd
verify the final logic. Sounds like a nightmare, which is why nobody
has got it to work very well.

--

John Larkin, President Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

John Larkin · Mar 8, 2012

On Thu, 8 Mar 2012 11:14:18 -0800 (PST), "langwadt@fonz.dk"
<langwadt@fonz.dk> wrote:

On 8 Mar., 17:50, Jim Thompson <To-Email-Use-The-Envelope-I...@On-My-
Web-Site.com> wrote:
On Thu, 08 Mar 2012 08:38:49 -0800, John Larkin

jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Thu, 08 Mar 2012 08:53:14 -0700, Jim Thompson
To-Email-Use-The-Envelope-I...@On-My-Web-Site.com> wrote:

On Tue, 06 Mar 2012 21:54:41 -0800, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:

On Tue, 06 Mar 2012 19:30:48 -0600, John Fields
jfie...@austininstruments.com> wrote:

[snip]
---
Ah, but there's yet more to come, illustrating how the lot of you who
can't make decisions between clock transitions are crippled.

Synchronous logic makes decisions between clocks, namely executes the
combinational logic that maps the current system state into the next
one. But it doesn't *act* on those decisions until they are stable,
and then only at the next clock. It's not the only way to design
logic, but it's the only practical way to design reliable logic of any
complexity, as your circuit bugs demonstrate.

Wikipedia has an article on async logic, and includes a long list of
async computer designs that never made it to production. Intel among
others has dabbled in async design and there are rumors that some
sections of some of their CPUs are async logic. Also rumors that an
async x86 design was scrapped in 1997.

Stay tuned...

Can't wait.

I'm certainly no logician, but surfing on "async logic" brings up some
interesting discussion that async can result in 40% power savings, but
takes more gates to do so. Considering the continual reduction in
ASIC feature size, considerable effort is in play for using async in
portable devices and in medical implants. The biggest impediment
right now to that development is the lack of async synthesis tools.

...Jim Thompson

That's been the problem for decades. Synchronous logic synthesis and
analysis separates the issue of logic correctness (pure state machine
stuff) from the issue of timing analysis, namely how fast can you
clock it reliably. Pipelining is a major tool to fix the problem of
the combinational logic limiting clock rates, but pipelined logic is
still just logic.

Async logic tangles the logic functionality with the speed issues. I'd
imagine that the simulation burden explodes when you do async logic:
what had been logical simulation becomes essentially analog
simulation.

Not so. Logic simulation remains logic simulation. Take the student
version of PSpice for a test drive and see how the logic simulator
works... it'll spit out all the hazards in a nice list.

for that specific implementation

I would imagine, at least for analysis, that VHDL and Verilog will
continue to work. Synthesis is the difficulty.

VHDL and Verilog is description language you can describe pretty much
anything you like
What you'll be analyzing/simulating will at best be a behavioral model
with some delay thrown in.

when you start Synthesis all bets will be off, logic might be
optimized away
implemented as lookup tables etc. etc.

Even if you basically write a netlist of instantiated primitives you
can't
always be sure what you get

Imagine simulating an analog circuit that has a billion
transistors and thousands of inputs and outputs. Now do that over Vcc
and process variations and temperature.

Billions, and billions, and billions... ;-)

Xilinxs latest show off mega FPGA is 6.8billion transistors ...

-Lasse

I was at a show a couple years ago and I saw a PCB that had 16
high-end Xilinx chips, which were about $6K each at the time. The
product was a hardware-based logic simulator, with a typical config
having a bunch of these boards inside.

And that was to simulate *synchronous* logic!

--

John Larkin, President
Highland Technology, Inc

jlarkin at highlandtechnology dot com
http://www.highlandtechnology.com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom laser controllers
Photonics and fiberoptic TTL data links
VME thermocouple, LVDT, synchro acquisition and simulation

langwadt@fonz.dk · Mar 8, 2012

On 8 Mar., 17:50, Jim Thompson <To-Email-Use-The-Envelope-I...@On-My-
Web-Site.com> wrote:

On Thu, 08 Mar 2012 08:38:49 -0800, John Larkin

jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Thu, 08 Mar 2012 08:53:14 -0700, Jim Thompson
To-Email-Use-The-Envelope-I...@On-My-Web-Site.com> wrote:

On Tue, 06 Mar 2012 21:54:41 -0800, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:

On Tue, 06 Mar 2012 19:30:48 -0600, John Fields
jfie...@austininstruments.com> wrote:

[snip]
---
Ah, but there's yet more to come, illustrating how the lot of you who
can't make decisions between clock transitions are crippled.

Synchronous logic makes decisions between clocks, namely executes the
combinational logic that maps the current system state into the next
one. But it doesn't *act* on those decisions until they are stable,
and then only at the next clock. It's not the only way to design
logic, but it's the only practical way to design reliable logic of any
complexity, as your circuit bugs demonstrate.

Wikipedia has an article on async logic, and includes a long list of
async computer designs that never made it to production. Intel among
others has dabbled in async design and there are rumors that some
sections of some of their CPUs are async logic. Also rumors that an
async x86 design was scrapped in 1997.

Stay tuned...

Can't wait.

I'm certainly no logician, but surfing on "async logic" brings up some
interesting discussion that async can result in 40% power savings, but
takes more gates to do so. Considering the continual reduction in
ASIC feature size, considerable effort is in play for using async in
portable devices and in medical implants. The biggest impediment
right now to that development is the lack of async synthesis tools.

...Jim Thompson

That's been the problem for decades. Synchronous logic synthesis and
analysis separates the issue of logic correctness (pure state machine
stuff) from the issue of timing analysis, namely how fast can you
clock it reliably. Pipelining is a major tool to fix the problem of
the combinational logic limiting clock rates, but pipelined logic is
still just logic.

Async logic tangles the logic functionality with the speed issues. I'd
imagine that the simulation burden explodes when you do async logic:
what had been logical simulation becomes essentially analog
simulation.

Not so. Logic simulation remains logic simulation. Take the student
version of PSpice for a test drive and see how the logic simulator
works... it'll spit out all the hazards in a nice list.

for that specific implementation

I would imagine, at least for analysis, that VHDL and Verilog will
continue to work. Synthesis is the difficulty.

VHDL and Verilog is description language you can describe pretty much
anything you like
What you'll be analyzing/simulating will at best be a behavioral model
with some delay thrown in.

when you start Synthesis all bets will be off, logic might be
optimized away
implemented as lookup tables etc. etc.

Even if you basically write a netlist of instantiated primitives you
can't
always be sure what you get

Imagine simulating an analog circuit that has a billion
transistors and thousands of inputs and outputs. Now do that over Vcc
and process variations and temperature.

Billions, and billions, and billions... ;-)

Xilinxs latest show off mega FPGA is 6.8billion transistors ...

-Lasse

petrus bitbyter · Mar 9, 2012

"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> schreef in
bericht news:3fphl7tp9vqh0iucqsonvbrbmk1bum185r@4ax.com...

On Thu, 08 Mar 2012 09:50:25 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Thu, 08 Mar 2012 08:38:49 -0800, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Thu, 08 Mar 2012 08:53:14 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Tue, 06 Mar 2012 21:54:41 -0800, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Tue, 06 Mar 2012 19:30:48 -0600, John Fields
jfields@austininstruments.com> wrote:

[snip]
---
Ah, but there's yet more to come, illustrating how the lot of you who
can't make decisions between clock transitions are crippled.

Synchronous logic makes decisions between clocks, namely executes the
combinational logic that maps the current system state into the next
one. But it doesn't *act* on those decisions until they are stable,
and then only at the next clock. It's not the only way to design
logic, but it's the only practical way to design reliable logic of any
complexity, as your circuit bugs demonstrate.

Wikipedia has an article on async logic, and includes a long list of
async computer designs that never made it to production. Intel among
others has dabbled in async design and there are rumors that some
sections of some of their CPUs are async logic. Also rumors that an
async x86 design was scrapped in 1997.

Stay tuned...

Can't wait.

I'm certainly no logician, but surfing on "async logic" brings up some
interesting discussion that async can result in 40% power savings, but
takes more gates to do so. Considering the continual reduction in
ASIC feature size, considerable effort is in play for using async in
portable devices and in medical implants. The biggest impediment
right now to that development is the lack of async synthesis tools.

...Jim Thompson

That's been the problem for decades. Synchronous logic synthesis and
analysis separates the issue of logic correctness (pure state machine
stuff) from the issue of timing analysis, namely how fast can you
clock it reliably. Pipelining is a major tool to fix the problem of
the combinational logic limiting clock rates, but pipelined logic is
still just logic.

Async logic tangles the logic functionality with the speed issues. I'd
imagine that the simulation burden explodes when you do async logic:
what had been logical simulation becomes essentially analog
simulation.

Not so. Logic simulation remains logic simulation. Take the student
version of PSpice for a test drive and see how the logic simulator
works... it'll spit out all the hazards in a nice list.

I would imagine, at least for analysis, that VHDL and Verilog will
continue to work. Synthesis is the difficulty.

VHDL is not an analysis language, it's a logic description language.
Actual gates and flops are synthesized downstream, with other tools,
and may look very different from the VHDL when it's actually mapped
into specific hardware.

There are VHDL simulation programs, but they usually work from the
VHDL itself, not the synthesized logic. What we usually do is sim at
VHDL level and do static timing analysis (which is ignorant of the
logic intent) after logic synthesis, and hope that the logic synthesis
stuff worked.

One could write an async logic design in VHDL - just don't clock
anything - but I don't know where you'd go from that, or how you'd
verify the final logic. Sounds like a nightmare, which is why nobody
has got it to work very well.

--

John Larkin, President Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

Down at the transistor level it's all analog. The combinatorials like the
gates can be considered analog and simulated that way but there's hardly a
thing to gain. Once you're using feedback building fliplops and other
sequential elements, analog simulation become more difficult though not
impossible. At this level the elements are still asynchronous but can be
used to build synchronous circuits. You can bet, the logic diagrams of the
internals of synchrounous counters and the like (hopefully) describe the
function, not the internal design. (Which is not uncommon in analog circuits
as well.) I'm not certain to what limit you can use analog simulation for
digital circuits these days, but it's clear that even a simple small micro
cannot be simulated this way. I heard rumours last year about design
software to build asynchronous sequential circuits, faster then the
synchronous counterparts, but I couldn't find it and the rumour died.

petrus bitbyter

Jim Thompson · Mar 11, 2012

On Sun, 11 Mar 2012 12:57:04 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 11 Mar 2012 14:01:09 -0500, John Fields
jfields@austininstruments.com> wrote:

[snip]

So, even though the logic between CARRY IN and CARRY OUT may be
combinatorial, it's driven synchronously, so its negative output will
always bear a fixed relationship, in time, to the positive going edge
of the external clock.

You have broken the synchronous nature of the carry chain - and of the
counter's internal logic - by feeding U6 carry in from the
asynchronous comparator output, splattering asynchronous levels all
over the place. You are doing this just to be peverse, to prove
somehow that hairball logic is a good thing. Jim approves.

Nope. Jim has no opinion, since I am not a logic designer and never
claimed to be.

I do approve of Fields jerking you around, though it's getting
tiresome. You are indeed suffering from brachycephalic rectumitis
(otherwise known as "with big head up butt"

, and seem hell-bent to
dominate this group, preventing all real circuit discussion...
claiming nothing can work but what you scribble (and fail to prove).

So I'm contemplating pulling a Woodgate and giving only advice on the
LTspice group where it'll be appreciated.

===============================================================
|| ||
|| I'll also be available, when time allows, to help people ||
|| who wish to contact me privately... use the "Envelope" ||
|| symbol on my website. ||
|| ||
===============================================================

You are treating the PE inputs of the counters as if they are edge
triggered. They are not. If you assert PE for 1.4 microseconds, what
gets jammed into U7/U9 is what's at their inputs at the *end* of the
1.4 usec. As I've shown, that can be wrong. You ended your timing
diagram *before* the hazard. You are hiding from the hazards because
you don't want to see them. Jim approves.

See! You even go out of your way to prove that you are fully infected
with brachycephalic rectumitis (otherwise known as "with big head up
butt"

John Larkin · Mar 11, 2012

On Sun, 11 Mar 2012 13:25:58 -0700, Jim Thompson
<To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Sun, 11 Mar 2012 12:57:04 -0700, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 11 Mar 2012 14:01:09 -0500, John Fields
jfields@austininstruments.com> wrote:

[snip]

So, even though the logic between CARRY IN and CARRY OUT may be
combinatorial, it's driven synchronously, so its negative output will
always bear a fixed relationship, in time, to the positive going edge
of the external clock.

You have broken the synchronous nature of the carry chain - and of the
counter's internal logic - by feeding U6 carry in from the
asynchronous comparator output, splattering asynchronous levels all
over the place. You are doing this just to be peverse, to prove
somehow that hairball logic is a good thing. Jim approves.

Nope. Jim has no opinion, since I am not a logic designer and never
claimed to be.

I do approve of Fields jerking you around, though it's getting
tiresome. You are indeed suffering from brachycephalic rectumitis
(otherwise known as "with big head up butt" ,

You and JF constantly mention things anal and penile. Enjoy!

--

John Larkin, President Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

Jim Thompson · Mar 11, 2012

On Sun, 11 Mar 2012 14:15:50 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 11 Mar 2012 13:25:58 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Sun, 11 Mar 2012 12:57:04 -0700, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 11 Mar 2012 14:01:09 -0500, John Fields
jfields@austininstruments.com> wrote:

[snip]

So, even though the logic between CARRY IN and CARRY OUT may be
combinatorial, it's driven synchronously, so its negative output will
always bear a fixed relationship, in time, to the positive going edge
of the external clock.

You have broken the synchronous nature of the carry chain - and of the
counter's internal logic - by feeding U6 carry in from the
asynchronous comparator output, splattering asynchronous levels all
over the place. You are doing this just to be peverse, to prove
somehow that hairball logic is a good thing. Jim approves.

Nope. Jim has no opinion, since I am not a logic designer and never
claimed to be.

I do approve of Fields jerking you around, though it's getting
tiresome. You are indeed suffering from brachycephalic rectumitis
(otherwise known as "with big head up butt" ,

You and JF constantly mention things anal and penile. Enjoy!

John Fields · Mar 11, 2012

On Sun, 11 Mar 2012 14:15:50 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 11 Mar 2012 13:25:58 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Sun, 11 Mar 2012 12:57:04 -0700, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 11 Mar 2012 14:01:09 -0500, John Fields
jfields@austininstruments.com> wrote:

[snip]

So, even though the logic between CARRY IN and CARRY OUT may be
combinatorial, it's driven synchronously, so its negative output will
always bear a fixed relationship, in time, to the positive going edge
of the external clock.

You have broken the synchronous nature of the carry chain - and of the
counter's internal logic - by feeding U6 carry in from the
asynchronous comparator output, splattering asynchronous levels all
over the place. You are doing this just to be peverse, to prove
somehow that hairball logic is a good thing. Jim approves.

Nope. Jim has no opinion, since I am not a logic designer and never
claimed to be.

I do approve of Fields jerking you around, though it's getting
tiresome. You are indeed suffering from brachycephalic rectumitis
(otherwise known as "with big head up butt" ,

You and JF constantly mention things anal and penile. Enjoy!

---
When we talk about little pricks like you who are such big assholes,
how can it be avoided?

--
JF

John Larkin · Mar 11, 2012

On Sun, 11 Mar 2012 16:24:34 -0500, John Fields
<jfields@austininstruments.com> wrote:

On Sun, 11 Mar 2012 14:15:50 -0700, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 11 Mar 2012 13:25:58 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Sun, 11 Mar 2012 12:57:04 -0700, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 11 Mar 2012 14:01:09 -0500, John Fields
jfields@austininstruments.com> wrote:

[snip]

So, even though the logic between CARRY IN and CARRY OUT may be
combinatorial, it's driven synchronously, so its negative output will
always bear a fixed relationship, in time, to the positive going edge
of the external clock.

You have broken the synchronous nature of the carry chain - and of the
counter's internal logic - by feeding U6 carry in from the
asynchronous comparator output, splattering asynchronous levels all
over the place. You are doing this just to be peverse, to prove
somehow that hairball logic is a good thing. Jim approves.

Nope. Jim has no opinion, since I am not a logic designer and never
claimed to be.

I do approve of Fields jerking you around, though it's getting
tiresome. You are indeed suffering from brachycephalic rectumitis
(otherwise known as "with big head up butt" ,

You and JF constantly mention things anal and penile. Enjoy!

---
When we talk about little pricks like you who are such big assholes,
how can it be avoided?

There you go again.

--

John Larkin, President Highland Technology Inc
www.highlandtechnology.com jlarkin at highlandtechnology dot com

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

John Fields · Mar 12, 2012

On Sun, 11 Mar 2012 14:31:05 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 11 Mar 2012 16:24:34 -0500, John Fields
jfields@austininstruments.com> wrote:

On Sun, 11 Mar 2012 14:15:50 -0700, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 11 Mar 2012 13:25:58 -0700, Jim Thompson
To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote:

On Sun, 11 Mar 2012 12:57:04 -0700, John Larkin
jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

On Sun, 11 Mar 2012 14:01:09 -0500, John Fields
jfields@austininstruments.com> wrote:

[snip]

So, even though the logic between CARRY IN and CARRY OUT may be
combinatorial, it's driven synchronously, so its negative output will
always bear a fixed relationship, in time, to the positive going edge
of the external clock.

You have broken the synchronous nature of the carry chain - and of the
counter's internal logic - by feeding U6 carry in from the
asynchronous comparator output, splattering asynchronous levels all
over the place. You are doing this just to be peverse, to prove
somehow that hairball logic is a good thing. Jim approves.

Nope. Jim has no opinion, since I am not a logic designer and never
claimed to be.

I do approve of Fields jerking you around, though it's getting
tiresome. You are indeed suffering from brachycephalic rectumitis
(otherwise known as "with big head up butt" ,

You and JF constantly mention things anal and penile. Enjoy!

---
When we talk about little pricks like you who are such big assholes,
how can it be avoided?

There you go again.

---
And why shouldn't I?
--
JF

muhaned alzedi · Mar 29, 2012

thank u for reply ,but i want sensor for(transfer the maniacal motion to electric ) like microphone .

hrh1818 · Mar 30, 2012

On Mar 28, 11:27 pm, dakup...@gmail.com wrote:

Could some electronics guru please clarify
this a bit ? I am thinking about making a
solar cell phone charger. Cell phones normally
use Li-ion batteries, but digging around on
the Internet, I see people using a solar charger
to charge Ni-Cd batteries, and then using the
latter to charge the actual cell phone battery.
In my spare time, I have desined and built a Ni-Cd
battery charger powered by a 10.5 V(max) solar
panel. It charges 4 Ni-Cd cells for a 20 white
LED solar lamp and works fine so far.
So, is there some charger design that will
directly charge a Li-ion battery ? I am looking
around for a simple design, preferably using
simple ICs as the LM317. Or is the current design
sufficient ?
Any hints, suggestions would be greatly appreciated.
Thanks in advance.

There are a lot solar power battery chargers in the market with a USB
connector. This means they can charge most any pone that is charged
via a USB connector. I say most because some phones ave high
charging current requirements, Some of the low cost models may not
work with phones with high charging current requirements.
For some examples of solar power cell phone battery chargers see:
<http://www.amazon.com/s/ref=nb_sb_ss_i_0_14?url=search-alias
%3Dmobile&field-keywords=solar+battery+charger&sprefix=solar+battery+
%2Cmobile%2C154>

For higher priced models see:
<http://www.amazon.com/s/ref=sr_gnr_aps?rh=i%3Aaps%2Ck
%3Asoladec&keywords=soladec&ie=UTF8&qid=1333069434>

Howard

Robert Macy · Mar 30, 2012

On Mar 29, 2:54 pm, muhaned alzedi <muhaned.2...@gmail.com> wrote:

thank u for reply ,but i want sensor for(transfer the maniacal motion to electric ) like microphone .

a high speed altimeter.

Robert Macy · Mar 30, 2012

On Mar 29, 6:21 am, George Herold <gher...@teachspin.com> wrote:

On Mar 29, 8:57 am, Robert Macy <robert.a.m...@gmail.com> wrote:

On Mar 28, 3:07 pm, muhaned.2...@gmail.com wrote:

i want the best microphone (for sensor) for the low frequency,,,, what is it name ?

Pressure Sensor

Anyone ever tried using a speaker as detector?

George H.

works great for speech. Used to be used in those old single duplex
intercom systems.

I know the voltage out of the speaker for low frequency is low due to
the dB/dt efffect. There must be some point where low frequency
doesn't move the cone very well as the cone is smaller and smaller
section of wavelength. So probably a double roll-off on the low end?

mike · Apr 2, 2012

On 3/28/2012 10:27 PM, dakupoto@gmail.com wrote:

Could some electronics guru please clarify
this a bit ? I am thinking about making a
solar cell phone charger. Cell phones normally
use Li-ion batteries, but digging around on
the Internet, I see people using a solar charger
to charge Ni-Cd batteries, and then using the
latter to charge the actual cell phone battery.
In my spare time, I have desined and built a Ni-Cd
battery charger powered by a 10.5 V(max) solar
panel. It charges 4 Ni-Cd cells for a 20 white
LED solar lamp and works fine so far.
So, is there some charger design that will
directly charge a Li-ion battery ? I am looking
around for a simple design, preferably using
simple ICs as the LM317. Or is the current design
sufficient ?
Any hints, suggestions would be greatly appreciated.
Thanks in advance.

Solar cell phone chargers are novelty items for those
who haven't done the math. For the six people in the world
who like to do extended wilderness camping on sunny days within range
of a cell tower with uninterrupted tweeting,
solar makes a lot of sense. For the rest of us with access
to grid power or an automobile, not so much.

Do the math. How long are you willing to wait in the sun
for the phone to charge? Do you care if you can't charge
on an overcast day? How big a panel are you willing
to pack around.

Suggest you use the existing setup to charge NiCd cells
and stick those into a dedicated cellphone auxiliary USB charger.
Gonna be far cheaper too. With a pocket full of charged
nicads, you can make your phone work, even at night.

You use a lot of different terms. Perhaps you believe
they're equivalent, but it's difficult to know
what you really want.

Charging a lithium battery directly is difficult
because you risk damaging the battery of setting it,
and yourself, on fire.
You need VERY tight charge control. And all lithium
batteries are not the same.
You can buy lithium ion batteries with built-in protection
to minimize this problem, but that's only a fail-safe...
you still want carefully controlled charge parameters.

If you want to remove the battery from your phone
and charge it, there's usually protection built into that
battery. You still need to know EXACTLY what technology
is being used.
Just connecting to the terminals is not simple.

Charging via usb can be accomplished with dedicated emergency
chargers that run on AA batteries.

hamilton · Apr 2, 2012

On 3/29/2012 1:26 AM, Klaus Kragelund wrote:

On 28 Mar., 22:01, Klaus Kragelund<klausk...@hotmail.com> wrote:
On 28 Mar., 19:10, linnix<m...@linnix.info-for.us> wrote:

On Mar 28, 2:55 am, Klaus Kragelund<klausk...@hotmail.com> wrote:

Hi

For a new design I am looking for cheap LCD modules:

64x64 dots (or more)
16mm x 20mm outline
SPI, I2C, parallel, I don't care
Backlight

The source must be stable, so we don't run into obsolescence problems

Anyone come accross something below 3-5 USD in large quantities?

How large? If in Ks, we can make them Contact us at linnix at live
dot com.

I have just send you an email, thanks - Skjul tekst i anfřrselstegn -

- Vis tekst i anfřrselstegn -

For others that may be curious, found this:

http://dk.mouser.com/ProductDetail/Varitronix/COG-C144MVGI-08/?qs=sGAEpiMZZMvkC18yXH9iIlSS2qf0I4f7FEXGi1Eq4z4%3D

Good quality and seems it should sell for about 3 USD

Regards

Klaus
As per this link, 3 EURO != 3 USD

Winston · Apr 2, 2012

George Herold wrote:

On Mar 29, 8:57 am, Robert Macy<robert.a.m...@gmail.com> wrote:
On Mar 28, 3:07 pm, muhaned.2...@gmail.com wrote:

i want the best microphone (for sensor) for the low frequency,,,, what is it name ?

Pressure Sensor

Anyone ever tried using a speaker as detector?

IIRC, lots of cheap house intercoms used speakers as microphones.

--Winston

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