Discrete IF limiter for GPS Rx

A

Andrew Holme

Guest
I need a limiting IF amplifier with 2MHz -3dB bandwidth. I'm flexible on
the exact centre frequency; but around 20 MHz was my plan.

In the 80s and 90s, there were numerous FM IF chips; but they're all going
obsolete now. The AD8306 is nice; but very expensive and is likely to
pickup digital noise and other nasties on my board, all the way up to 1 GHz,
because it has no selectivity. The LT6402 is differential, has fixed gain
and allows a tuned circuit across the output. I was thinking about using a
cascade of them; but this is a hobby project and I don't like QFN packages.

I was wondering how practical it might be to do this discretely using
matched-pairs. I am talking about a cascade of long-tailed pairs with
parallel tuned circuits between the collectors. This is a lot cheaper and
simpler than a cascade of LT6402. Is that practical? Below is an LTSpice
demo of what I have in mind. I would obviously include good PSU decoupling,
a solid ground plane underneath and a balanced symmetrical layout.

The project is a single-conversion GPS receiver with fractional-N PLL
generating a first LO of (say) 1555.42 MHz and this 20 MHz IF limter acting
as a 1-bit A/D quantizer into an FPGA. There would be a +30dB gain LNA
(with 2MHz BW SAW filter) before the mixer.

Any advice?

TIA

Version 4
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On Sun, 14 Nov 2010 14:01:32 -0000, "Andrew Holme" <ah@nospam.com>
wrote:

I need a limiting IF amplifier with 2MHz -3dB bandwidth. I'm flexible on
the exact centre frequency; but around 20 MHz was my plan.

The project is a single-conversion GPS receiver with fractional-N PLL
generating a first LO of (say) 1555.42 MHz and this 20 MHz IF limter acting
as a 1-bit A/D quantizer into an FPGA. There would be a +30dB gain LNA
(with 2MHz BW SAW filter) before the mixer.
Click to expand...
Are you really trying to run the nominally 1.023 MHz wide DSSS signal
through the limiter ? That would make sense with exactly one DSSS
sequence within the frequency band and very strong signals.

However, there are several sequences within that band from different
satellites and also other interference signals. The thermal noise for
the 2 MHz bandwidth would most likely be stronger than the satellite
signal, thus the limiter would be captured by noise, not by the
signal.

AGC and limiters make sense _after_ the despreading from 1.023 MHz to
1 kHz after proper low pass filtering.
 
"Paul Keinanen" <keinanen@sci.fi> wrote in message
news:scrvd6dkdbl89c2gj9720cq4mfn0jqnl8v@4ax.com...
On Sun, 14 Nov 2010 14:01:32 -0000, "Andrew Holme" <ah@nospam.com
wrote:

I need a limiting IF amplifier with 2MHz -3dB bandwidth. I'm flexible on
the exact centre frequency; but around 20 MHz was my plan.

The project is a single-conversion GPS receiver with fractional-N PLL
generating a first LO of (say) 1555.42 MHz and this 20 MHz IF limter
acting
as a 1-bit A/D quantizer into an FPGA. There would be a +30dB gain LNA
(with 2MHz BW SAW filter) before the mixer.

Are you really trying to run the nominally 1.023 MHz wide DSSS signal
through the limiter ? That would make sense with exactly one DSSS
sequence within the frequency band and very strong signals.

However, there are several sequences within that band from different
satellites and also other interference signals. The thermal noise for
the 2 MHz bandwidth would most likely be stronger than the satellite
signal, thus the limiter would be captured by noise, not by the
signal.

AGC and limiters make sense _after_ the despreading from 1.023 MHz to
1 kHz after proper low pass filtering.
Click to expand...
It works, even if you limit _before_ despreading. I got the idea from here:
http://lea.hamradio.si/~s53mv/navsats/theory.html

and I did a C++ simulation (of 3 satellites @ -130 dBm each plus white
gaussian noise @ -111 dBm) which seems to confirm it:
http://www.holmea.demon.co.uk/Misc/Costas.cpp

see also:
http://www.research.telcordia.com/society/TacCom/papers98/21_07i.pdf
 
Paul Keinanen wrote:

I need a limiting IF amplifier with 2MHz -3dB bandwidth. I'm flexible on
the exact centre frequency; but around 20 MHz was my plan.

The project is a single-conversion GPS receiver with fractional-N PLL
generating a first LO of (say) 1555.42 MHz and this 20 MHz IF limter acting
as a 1-bit A/D quantizer into an FPGA.

AGC and limiters make sense _after_ the despreading from 1.023 MHz to
1 kHz after proper low pass filtering.
Click to expand...
In fact, many GPS modules clip the bandpass signal before despreading.
Albeit being unoptimal, this approach is pretty standard because of
simplicity. That's why GPS is so easily jammed by CW interference.

The optimal approach would be limiting at some level before and after
the despreading. The pre-limiting would clip the pulse interferrors
before they get smeared.

Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com
 
On Sun, 14 Nov 2010 14:01:32 -0000, "Andrew Holme" <ah@nospam.com>
wrote:

I need a limiting IF amplifier with 2MHz -3dB bandwidth. I'm flexible on
the exact centre frequency; but around 20 MHz was my plan.
Click to expand...
I was doing such an IF, at 60MHz, with a mid-60's process... military
project.

Commercial equivalent was MC1550, followed by the MC1590.

I wonder if you couldn't use MC1596, or equivalent, multiplier, but
simply cock the upper section by 200mV, eliminating its effect (other
than perhaps a noise source)?

In the 80s and 90s, there were numerous FM IF chips; but they're all going
obsolete now. The AD8306 is nice; but very expensive and is likely to
pickup digital noise and other nasties on my board, all the way up to 1 GHz,
because it has no selectivity. The LT6402 is differential, has fixed gain
and allows a tuned circuit across the output. I was thinking about using a
cascade of them; but this is a hobby project and I don't like QFN packages.

I was wondering how practical it might be to do this discretely using
matched-pairs. I am talking about a cascade of long-tailed pairs with
parallel tuned circuits between the collectors. This is a lot cheaper and
simpler than a cascade of LT6402. Is that practical?
Click to expand...
That will work. Your tank approach keeps offsets from accumulating.

Below is an LTSpice
demo of what I have in mind. I would obviously include good PSU decoupling,
a solid ground plane underneath and a balanced symmetrical layout.

The project is a single-conversion GPS receiver with fractional-N PLL
generating a first LO of (say) 1555.42 MHz and this 20 MHz IF limter acting
as a 1-bit A/D quantizer into an FPGA. There would be a +30dB gain LNA
(with 2MHz BW SAW filter) before the mixer.

Any advice?

TIA

Version 4
SHEET 1 1764 680
WIRE 224 -96 64 -96
[snip]
SYMATTR Value2 AC 1
TEXT -674 24 Left 0 !.tran 0 11u 10u 1n
TEXT -672 -16 Left 0 !.param RC=270, RE=180, L=470n, C=100p
Click to expand...
...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

You VOTED for Obama. Why are you surprised you GOT Hitler?
 
On 11/14/2010 06:24 AM, Paul Keinanen wrote:
On Sun, 14 Nov 2010 14:01:32 -0000, "Andrew Holme"<ah@nospam.com
wrote:

I need a limiting IF amplifier with 2MHz -3dB bandwidth. I'm flexible on
the exact centre frequency; but around 20 MHz was my plan.

The project is a single-conversion GPS receiver with fractional-N PLL
generating a first LO of (say) 1555.42 MHz and this 20 MHz IF limter acting
as a 1-bit A/D quantizer into an FPGA. There would be a +30dB gain LNA
(with 2MHz BW SAW filter) before the mixer.

Are you really trying to run the nominally 1.023 MHz wide DSSS signal
through the limiter ? That would make sense with exactly one DSSS
sequence within the frequency band and very strong signals.

However, there are several sequences within that band from different
satellites and also other interference signals. The thermal noise for
the 2 MHz bandwidth would most likely be stronger than the satellite
signal, thus the limiter would be captured by noise, not by the
signal.

AGC and limiters make sense _after_ the despreading from 1.023 MHz to
1 kHz after proper low pass filtering.
Click to expand...
The standard non-rugged GPS receiver model is to bring the signal in
from the antenna and run it through a 1-bit ADC*, then do all the
processing in the digital domain. Running the signal through a limiting
amp is immaterial to the behavior of the 1-bit ADC and simplifies the
circuitry.

Like Vladimir says, this makes the signal susceptible to CW
interference. But folks buy their GPS receivers anyway, so it must be
all right -- right?

* Yes, "Comparator" -- but the literature always calls it a "one-bit
ADC, so that's what I'm doing, OK?"

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
On 11/14/2010 06:01 AM, Andrew Holme wrote:
I need a limiting IF amplifier with 2MHz -3dB bandwidth. I'm flexible on
the exact centre frequency; but around 20 MHz was my plan.

In the 80s and 90s, there were numerous FM IF chips; but they're all going
obsolete now. The AD8306 is nice; but very expensive and is likely to
pickup digital noise and other nasties on my board, all the way up to 1 GHz,
because it has no selectivity. The LT6402 is differential, has fixed gain
and allows a tuned circuit across the output. I was thinking about using a
cascade of them; but this is a hobby project and I don't like QFN packages.

I was wondering how practical it might be to do this discretely using
matched-pairs. I am talking about a cascade of long-tailed pairs with
parallel tuned circuits between the collectors. This is a lot cheaper and
simpler than a cascade of LT6402. Is that practical? Below is an LTSpice
demo of what I have in mind. I would obviously include good PSU decoupling,
a solid ground plane underneath and a balanced symmetrical layout.

The project is a single-conversion GPS receiver with fractional-N PLL
generating a first LO of (say) 1555.42 MHz and this 20 MHz IF limter acting
as a 1-bit A/D quantizer into an FPGA. There would be a +30dB gain LNA
(with 2MHz BW SAW filter) before the mixer.

Any advice?

The ARRL Handbook used to have limiting amplifiers in their "FM
Click to expand...
receivers" section. You might see if they have something.

There are also microwave amplifier chips that go down to that frequency
range, and if I recall correctly some of them will go into limiting
gracefully (some will be atrocious). That might be a fruitful place to
look.

At a 20MHz IF frequency you could almost do this with 2N3904s; I don't
think you need matched pairs if you're hard limiting, and a bit of
emitter degeneration before the long tail will get you a lot of "matching".

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html
 
On Sun, 14 Nov 2010 14:47:10 -0800, Tim Wescott <tim@seemywebsite.com>
wrote:

On 11/14/2010 06:24 AM, Paul Keinanen wrote:
On Sun, 14 Nov 2010 14:01:32 -0000, "Andrew Holme"<ah@nospam.com
wrote:

I need a limiting IF amplifier with 2MHz -3dB bandwidth. I'm flexible on
the exact centre frequency; but around 20 MHz was my plan.

The project is a single-conversion GPS receiver with fractional-N PLL
generating a first LO of (say) 1555.42 MHz and this 20 MHz IF limter acting
as a 1-bit A/D quantizer into an FPGA. There would be a +30dB gain LNA
(with 2MHz BW SAW filter) before the mixer.

Are you really trying to run the nominally 1.023 MHz wide DSSS signal
through the limiter ? That would make sense with exactly one DSSS
sequence within the frequency band and very strong signals.

However, there are several sequences within that band from different
satellites and also other interference signals. The thermal noise for
the 2 MHz bandwidth would most likely be stronger than the satellite
signal, thus the limiter would be captured by noise, not by the
signal.

AGC and limiters make sense _after_ the despreading from 1.023 MHz to
1 kHz after proper low pass filtering.

The standard non-rugged GPS receiver model is to bring the signal in
from the antenna and run it through a 1-bit ADC*, then do all the
processing in the digital domain. Running the signal through a limiting
amp is immaterial to the behavior of the 1-bit ADC and simplifies the
circuitry.

Like Vladimir says, this makes the signal susceptible to CW
interference. But folks buy their GPS receivers anyway, so it must be
all right -- right?

* Yes, "Comparator" -- but the literature always calls it a "one-bit
ADC, so that's what I'm doing, OK?"
Click to expand...
The difference between a 1-bit ADC and a comparator is that the ADC
output is properly synchronized to a clock. If you give the output of
a comparator to a digital circuit, the designer may not know how to
properly sample it, so you need a 1-bit ADC.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com
 
On Sun, 14 Nov 2010 15:33:49 -0800, Muzaffer Kal <kal@dspia.com>
wrote:

On Sun, 14 Nov 2010 14:47:10 -0800, Tim Wescott <tim@seemywebsite.com
wrote:

On 11/14/2010 06:24 AM, Paul Keinanen wrote:
On Sun, 14 Nov 2010 14:01:32 -0000, "Andrew Holme"<ah@nospam.com
wrote:

I need a limiting IF amplifier with 2MHz -3dB bandwidth. I'm flexible on
the exact centre frequency; but around 20 MHz was my plan.

The project is a single-conversion GPS receiver with fractional-N PLL
generating a first LO of (say) 1555.42 MHz and this 20 MHz IF limter acting
as a 1-bit A/D quantizer into an FPGA. There would be a +30dB gain LNA
(with 2MHz BW SAW filter) before the mixer.

Are you really trying to run the nominally 1.023 MHz wide DSSS signal
through the limiter ? That would make sense with exactly one DSSS
sequence within the frequency band and very strong signals.

However, there are several sequences within that band from different
satellites and also other interference signals. The thermal noise for
the 2 MHz bandwidth would most likely be stronger than the satellite
signal, thus the limiter would be captured by noise, not by the
signal.

AGC and limiters make sense _after_ the despreading from 1.023 MHz to
1 kHz after proper low pass filtering.

The standard non-rugged GPS receiver model is to bring the signal in
from the antenna and run it through a 1-bit ADC*, then do all the
processing in the digital domain. Running the signal through a limiting
amp is immaterial to the behavior of the 1-bit ADC and simplifies the
circuitry.

Like Vladimir says, this makes the signal susceptible to CW
interference. But folks buy their GPS receivers anyway, so it must be
all right -- right?

* Yes, "Comparator" -- but the literature always calls it a "one-bit
ADC, so that's what I'm doing, OK?"

The difference between a 1-bit ADC and a comparator is that the ADC
output is properly synchronized to a clock. If you give the output of
a comparator to a digital circuit, the designer may not know how to
properly sample it, so you need a 1-bit ADC.
Click to expand...
What modulation coding does GPS use?

...Jim Thompson
--
| James E.Thompson, CTO | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona 85048 Skype: Contacts Only | |
| Voice:(480)460-2350 Fax: Available upon request | Brass Rat |
| E-mail Icon at http://www.analog-innovations.com | 1962 |

You VOTED for Obama. Why are you surprised you GOT Hitler?
 
"Jim Thompson" <To-Email-Use-The-Envelope-Icon@On-My-Web-Site.com> wrote in
message news:kus0e6hqugiqlhsscjsno5o8r9sa9p7cs3@4ax.com...
On Sun, 14 Nov 2010 15:33:49 -0800, Muzaffer Kal <kal@dspia.com
wrote:

On Sun, 14 Nov 2010 14:47:10 -0800, Tim Wescott <tim@seemywebsite.com
wrote:

On 11/14/2010 06:24 AM, Paul Keinanen wrote:
On Sun, 14 Nov 2010 14:01:32 -0000, "Andrew Holme"<ah@nospam.com
wrote:

I need a limiting IF amplifier with 2MHz -3dB bandwidth. I'm flexible
on
the exact centre frequency; but around 20 MHz was my plan.

The project is a single-conversion GPS receiver with fractional-N PLL
generating a first LO of (say) 1555.42 MHz and this 20 MHz IF limter
acting
as a 1-bit A/D quantizer into an FPGA. There would be a +30dB gain
LNA
(with 2MHz BW SAW filter) before the mixer.

Are you really trying to run the nominally 1.023 MHz wide DSSS signal
through the limiter ? That would make sense with exactly one DSSS
sequence within the frequency band and very strong signals.

However, there are several sequences within that band from different
satellites and also other interference signals. The thermal noise for
the 2 MHz bandwidth would most likely be stronger than the satellite
signal, thus the limiter would be captured by noise, not by the
signal.

AGC and limiters make sense _after_ the despreading from 1.023 MHz to
1 kHz after proper low pass filtering.

The standard non-rugged GPS receiver model is to bring the signal in
from the antenna and run it through a 1-bit ADC*, then do all the
processing in the digital domain. Running the signal through a limiting
amp is immaterial to the behavior of the 1-bit ADC and simplifies the
circuitry.

Like Vladimir says, this makes the signal susceptible to CW
interference. But folks buy their GPS receivers anyway, so it must be
all right -- right?

* Yes, "Comparator" -- but the literature always calls it a "one-bit
ADC, so that's what I'm doing, OK?"

The difference between a 1-bit ADC and a comparator is that the ADC
output is properly synchronized to a clock. If you give the output of
a comparator to a digital circuit, the designer may not know how to
properly sample it, so you need a 1-bit ADC.

What modulation coding does GPS use?
Click to expand...
BPSK

Carrier * Data (50bps) * SpreadingCode (1.023Mbps)
 
"Andrew Holme" <ah@nospam.com> wrote in message
news:1ZRDo.76348$9k3.21513@newsfe24.ams2...
I need a limiting IF amplifier with 2MHz -3dB bandwidth. I'm flexible on
the exact centre frequency; but around 20 MHz was my plan.
[snip]
Click to expand...

Thanks for all the comments posted so far on this.

I've placed three versions of the LTSpice sim here
http://www.holmea.demon.co.uk/Misc/

Limiter2.asc was the original with parallel LC between collectors but not on
the last stage
Limiter4.asc has parallel LC on the last stage as well
Limiter6.asc is an alternative approach with series LC between emitters

2 & 4 have different component values. If I add parallel LC at the output
in version 2, it goes unstable. Maybe series LC between emitters is safer?
 
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