DGnd and AGnd?

[DaveC]

Some chips have separate Digital Grounds and Analog Grounds. Many data
sheets I've read simply say to ensure they are no more then a few
millivolts of each other. But can any one give me some advice on best
practice in regards to Shielding, PCB design, Power Sup issues? Or even why
they are separate pins on the chip, if we are to simply tie them together.

Thanks
DaveC

 

[Dirk Bruere at Neopax]

"DaveC" <bobason456@hotmail.com> wrote in message
news:Xns94B1AF93F9A1Aohirohotmailcom@202.20.93.13...

Some chips have separate Digital Grounds and Analog Grounds. Many data
sheets I've read simply say to ensure they are no more then a few
millivolts of each other. But can any one give me some advice on best
practice in regards to Shielding, PCB design, Power Sup issues? Or even
why
they are separate pins on the chip, if we are to simply tie them together.

Digital stuff is all on-off sharp transitions and power drain, which feeds
back into the power supply tracks as spikes.
Analogue can well do without such a dirty shared supply.

--
Dirk

The Consensus:-
The political party for the new millennium
http://www.theconsensus.org

 

[Mac]

On Fri, 19 Mar 2004 04:18:18 +0000, DaveC wrote:

Some chips have separate Digital Grounds and Analog Grounds. Many data
sheets I've read simply say to ensure they are no more then a few
millivolts of each other. But can any one give me some advice on best
practice in regards to Shielding, PCB design, Power Sup issues? Or even why
they are separate pins on the chip, if we are to simply tie them together.

Thanks
DaveC

I'm not sure I have a full and complete understanding. But typically, I
just follow the layout guidlines in the datasheet. In principal, you could
keep them separated by an inductor, but that can cause problems, too. In
particular, if you allow the analog ground to be separated (at RF) from
the digital ground, you can run in to a problem if any analog signal is
then routed adjacent to the dirty digital ground plane. On the other hand,
if you can create an island of "AGND" big enough so that the signal is
routed adjacent to it for the entire run, then that could be OK. For
example, if you have a DDS with an "AGND," and the output just goes to an
RF connector, you could keep the RF connector in the clean "AGND" island.
Note that you should ideally not cut up a ground plane to do this.
Instead, make "AGND" a fill on a signal layer.

Most EMC/EMI people I have talked to have suggested that it is better to
simply use a dirty ground than it is to cut up a ground or power plane. If
you do cut up a plane, don't route across the plane split. If you do route
across the plane split, use high-frequency bridging caps (e.g., 0603 X7R
ceramics) near the signal traces. But the EMI people's concern is passing
FCC limits, not a super low-noise signal. ;-)

--Mac

 

[Mike]

On Fri, 19 Mar 2004 04:18:18 GMT, DaveC wrote:

Some chips have separate Digital Grounds and Analog Grounds. Many data
sheets I've read simply say to ensure they are no more then a few
millivolts of each other. But can any one give me some advice on best
practice in regards to Shielding, PCB design, Power Sup issues? Or even why
they are separate pins on the chip, if we are to simply tie them together.

I don't know about best practice, but the reason we split them up on a chip
is that power and ground usually come into the chip through inductive bond
wires and get distributed over resistive aluminum wires with little
bypassing. The combination of those factors means that if all the ground
(or power) on a chip were to come in from the same pins, the analog
circuits could see supply and ground transients every time the digital and
IO circuits switch. In general, it takes a much larger transient to
adversely affect digital logic than it does to affect analog circuits, and
splitting up the analog and digital power and ground on chip is much easier
than trying to design analog circuits that are immune to transients.

The traces on a PC board are much wider and much thicker than the traces on
most integrated circuits, and tend to have much lower inductance. Large
bypass capacitors are also easy to add around a chip, but much more
difficult (or at least much more expensive) to add on-chip.

-- Mike --

 

[Richard Hosking]

DaveC wrote:

Some chips have separate Digital Grounds and Analog Grounds. Many data
sheets I've read simply say to ensure they are no more then a few
millivolts of each other. But can any one give me some advice on best
practice in regards to Shielding, PCB design, Power Sup issues? Or even why
they are separate pins on the chip, if we are to simply tie them together.

Thanks
DaveC

It is suggested that you dont join analog and digital grounds at more
than one point. In practice I have used a single ground plane with all
ground connections made to it by vias which are as close to the chip as
possible. Where several pins are grounded through one via, I dont mix
analog and digital grounds on the same via and I tend to use lots of
vias. Also we used lots of bypasses, separate analog and digital
supplies and power filtering. As I am not a professional designer with
access to multilayer boards at reasonable cost, I used double sided
boards with a single ground plane on the bottom, with the top layer
components for a DDS project (9854) and the microwave DDS/PLL project
(see QEX March). This gave acceptable performance with regard to digital
noise using the measurement gear we had (my old HP140 spec analyser and
John Miles' Tek 494AP). In practice noise sidebands were dominated by
VCO noise (which had its own quiet supply). There were some problems
with intermodulation at certain frequencies and clock combinations , but
we suspect this was due to radiated signals rather than power supplies
or grounds, though of course we are unable to prove this. We would have
to shield the relevant sections better, though ground plane design could
have been a factor.
I would be interested in comments

Richard

 

[Terry Given]

"Mike" <mike@nospam.com> wrote in message
news:l7s33ow49fld$.5eobusu6c6ag$.dlg@40tude.net...

On Fri, 19 Mar 2004 04:18:18 GMT, DaveC wrote:

Some chips have separate Digital Grounds and Analog Grounds. Many data
sheets I've read simply say to ensure they are no more then a few
millivolts of each other. But can any one give me some advice on best
practice in regards to Shielding, PCB design, Power Sup issues? Or even
why
they are separate pins on the chip, if we are to simply tie them
together.

I don't know about best practice, but the reason we split them up on a
chip
is that power and ground usually come into the chip through inductive bond
wires and get distributed over resistive aluminum wires with little
bypassing. The combination of those factors means that if all the ground
(or power) on a chip were to come in from the same pins, the analog
circuits could see supply and ground transients every time the digital and
IO circuits switch. In general, it takes a much larger transient to
adversely affect digital logic than it does to affect analog circuits, and
splitting up the analog and digital power and ground on chip is much
easier
than trying to design analog circuits that are immune to transients.

The traces on a PC board are much wider and much thicker than the traces
on
most integrated circuits, and tend to have much lower inductance. Large
bypass capacitors are also easy to add around a chip, but much more
difficult (or at least much more expensive) to add on-chip.

I think the single most useful thing any electronics engineer knows is the
LCR circuit. If you can work out from scratch the laplace-domain transfer
function of a circuit containing these three bits, in terms of the damping
factor (or Q=1/[2*damping] if you like) and resonant frequency, and know
what these things mean, then you can successfully analyse (and hence design,
rather than blindly follow ROT) almost every practical problem you run
across, be they switch mode power supply design, snubbers, pcb layout, emc
filtering etc.

Without going that far, a good grasp of 1st order fundamentals:

v=i*Z
i=C*dv/dt
v=L*di/dt

will allow you to work out the ROT yourself.

How? every part we use contains an LCR circuit, along with the device
itself. every wire is of course a resistor (unless its a superconductor).
And if there is current flowing in a wire there is a magnetic field, which
contains energy, so the wire is an inductor. The current flowing in the
series LR circuit that our simple wire just turned into causes a voltage
drop, and hey presto - where there is a potential difference there must be
an electric field, which contains energy, so the wire has a capacitor, too,
between the two ends.

in a lot of cases the inductance or capacitance of a wire is really small,
so we can ignore it, but as frequency rises the reactive impedance terms
tend to dominate.

In a lot of cases the resistance is so low (say an opamp circuit, with a few
mA flowing around) that we can ignore it too, but sometimes (a 5A power
supply say) we cant. Forget this, and circuit boards cook over time...and of
course at high frequency the resistance gets higher too, so it might become
an issue.....

In the case of a chip with separate analogue & digital grounds (say a
microprocessor with an A-D converter on board), we start by looking inside
the chip, where we find a lead frame (metal) and a bond wire (metal) off to
the actual silicon. So we have a dangly wire, which we know is a mixture of
series L and R, with some shunt C. which is important?

Resistance?
well, we look at the chip datasheet, and it says Icc=48mA (say). If we knew
the exact size of the bond wire and the material we could just calculate the
resistance directly, or we could ask Jim nicely and he'll tell us, but we
dont even need to do that. If supply voltage is 3.3V, then a noticeable
voltage error might be 0.1% (say a 10-bit ADC) or 3.3mV. This needs
3.3mV/48mA = 69mOhms resistance. lets guess 0.1mm diameter bond wire of
copper, thats 5mm long. R=rho*l/A = rho*5e-3/(pi*(1e-4)^2) =
rho*(5/pi)*1e-3/1e-8 = rho*(5/pi)*1e5. for copper rho = 20e-9 [Ohm-m] or so,
giving R=20e-9*(5/pi)*1e5 = (100/pi)*1e-4 = 3.2mOhms or so giving about
0.1mV of voltage drop, well below the 3.3mV of 1LSB, so we can ignore it

for a digital chip with several hundred mV of noise margin, this 0.1mV or so
IR drop is even less of an issue than with the ADC. Conclusion: resistance
of wires can pretty much be ignored in all low-power circuitry, especially
digital.

what about inductance? inductances below 1nH are pretty hard to make, and a
good guess for an upper limit might be about 30nH, so lets guess 5nH. If we
know what our maximum step-change in current is, di, and its rise/fall time
dt, we calculate v = L*di/dt. we dont really know di, but it will be < Icc
max, so use that. use our fastest edge rise/fall times that (hopefully) are
spec'd, say 10ns, to calculate v = 5e-9*48e-3/10e-9 = 24e-3 - hey thats
about 10x bigger than the resistive drop. at high frequencies series L tends
to dominate....

what about capacitance? all of these voltages are tiny - << 1V, so the
amount of energy stored will be very small (E=0.5*C*v^2 with v^2 <<<< 1 and
c small anyway) so we can probably ignore it, but we could make a guess -
10pF is quite a bit of stray capacitance, 1pF would be a reasonable guess.
i=CdV/dt, = 1e-12*24e-3/5e-9 = 4.8e-6 = 4.8uA which is a lot less than 48mA,
so the capacitance wont do much.

just from some guesstimate numbers we can see that the inductance of the
bond wire is the real biggy, because of the fast rise & fall times. So with
separate Agnd and Dgnd pins, chip designers seem to be ensuring the fast
digital switching currents dont flow through the same bond wire as the low
frequency current for the A-D converter. On our pcb, we can therefore just
join them both to our 0V plane.

If we dont have a solid copper 0V plane, we must join them with a wire -
repeat the above analysis to see where to put your decoupling caps, and you
will soon see that inductance dominates again, so "as close to the chip pins
as possible" seems to be the answer. And sure enough, on chips we see +3.3V
and 0V pins almost side by side, so we can conveniently place a cap directly
across them, which will "soak up" the high-frequency current spikes drawn by
the digital circuitry (0603 fits nicely). And should you use leaded or smt
caps....look at the wires, smt it is.....or at least leaded caps with the
wires as short as possible.

in other words, look at the physical circuit you just built, rather than the
schematic you printed on a bit of paper (J. Fluke jr wrote an entire book on
controlling conducted emissions by design that essentially just says that).
Look at where the current physically flows, and you can "find" most of the
so-called "parasitic" (we didnt want them, they are just there) components
by inspection alone. If you are really enthusiastic, cou can
guess/calculate/measure their actual values.

engineers who design circuitry that meets various emc standards basically do
exactly this - the emc standards make you look at frequencies well up above
30MHz, where the parasitics begin to dominate overall behaviour. RF
engineers pretty much never think in terms of an R, an L, a C....always at
least the RLC model. If the frequency is above 1GHz or so, a distributed
model is required which is even more complex - as well as their amplitude &
phase you have to consider the physical position of your signals with
respect to components)

 

[Reg Edwards]

There's no such thing as a good digital design engineer with his chip
catalogues.

Analogue RULES.

 

[Boris Mohar]

On Fri, 19 Mar 2004 10:14:39 +0000 (UTC), "Reg Edwards"
<g4fgq.regp@ZZZbtinternet.com> wrote:

There's no such thing as a good digital design engineer with his chip
catalogues.

Analogue RULES.

You posted this using an analog computer?

--

Boris Mohar

 

[Ken Smith]

In article <Xns94B1AF93F9A1Aohirohotmailcom@202.20.93.13>,
DaveC <bobason456@hotmail.com> wrote:

Some chips have separate Digital Grounds and Analog Grounds. Many data
sheets I've read simply say to ensure they are no more then a few
millivolts of each other. But can any one give me some advice on best
practice in regards to Shielding, PCB design, Power Sup issues? Or even why
they are separate pins on the chip, if we are to simply tie them together.

The basic ideas are:

The bypass capacitors should connect to the ground at or near the digital
ground so that large AC currents don't flow near the analog ground.

The op-amps etc should have their reference ground point brought to the
analog ground.

Idealy the analog ground and digital ground should only be interconnected
at the ADC chip so that no other currents flow in the analog ground.


--
--
kensmith@rahul.net forging knowledge

 

[Reg Edwards]

"Mike" wrote> Don't ridicule the digital guys for not knowing what you know.
They don't

need to. They aren't playing in the same sandbox.

========================

Sorry Mike, no offence intended.

 

[Mike]

On Fri, 19 Mar 2004 10:14:39 +0000 (UTC), Reg Edwards wrote:

There's no such thing as a good digital design engineer with his chip
catalogues.

Analogue RULES.

Ah, the old analog-digital wars again.

I switch hit, depending on the needs. Sure, analog rules. So does digital.

Modern digital IC design allows amazingly complex functions to be built
with an ease that's unheard of in analog. A relatively complex mixed-signal
IC with a few thousand transistors is roughly equivalent in work required
to hundreds of thousands, if not millions, of digital gates. The tools
allow a digital designer to move away from the level where they have to be
concerned about characteristics of gates and the parasitics and delays
between them to a level where they can concentrate much more on the
algorithms being implemented. That allows digital engineers to tackle
projects with far greater amounts of equivalent signal processing than
analog projects.

Don't ridicule the digital guys for not knowing what you know. They don't
need to. They aren't playing in the same sandbox.

-- Mike --

 

[MikeM]

DaveC wrote:

Some chips have separate Digital Grounds and Analog Grounds. Many data
sheets I've read simply say to ensure they are no more then a few
millivolts of each other.

But can any one give me some advice on best
practice in regards to Shielding, PCB design, Power Sup issues? Or even why
they are separate pins on the chip, if we are to simply tie them together.

This good-engineering paractice is called "Single Point Ground"

The principle idea is to never have the "noise" currents
flowing along traces carrying "signal" currents. If noise and
signal currents flow along a conductor, the impedance (ac or dc)
along the conductor couples one into the other.

Even though you eventually have to tie the two grounds together,
the WAY you tie them determines how much coupling will exist.

MIkeM

 

[Terry Given]

"Reg Edwards" <g4fgq.regp@ZZZbtinternet.com> wrote in message
news:c3f7o5$ran$1@sparta.btinternet.com...

"Mike" wrote> Don't ridicule the digital guys for not knowing what you
know.
They don't
need to. They aren't playing in the same sandbox.

========================

Sorry Mike, no offence intended.

I always liked this one:

why are analogue engineers smarter than digital engineers?
how hard is it to count to one.....

apples and hydaulics, really. A few years back a mate and I were amazed to
discover it was cost effective to replace a couple of lm339s and a few Rs &
Cs with an 8-pin PIC micro - no reset cct, no oscillator, 6 io pins in a
soic 8, and even analogue inputs....amazing

and then theres DSP - while you can build complex MIMO controllers with
analogue circuitry, yah wouldnt want to.....and TI make $5 dsp chips with
16x 1us ADCs

the problem of course with using a micro instead of analogue circuitry is
that once the circuit works, you have to write the software to make it all
function......

I spend a lot of time fixing other peoples designs, usually for emc
compliance, noise immunity or whatever. It is mostly when the digital people
dont realise they are in the analogue domain that the problems I see arise -
poor pcb layout most often.

What is really surprising is the amount of times I see all-digital comms
links with no real error detection (and correction), often not even parity.
The worst offenders use individual bit positions as control flags, thereby
ensuring that a bit-flip type of error will do the maximum harm. Have they
never heard of hamming distances? huffman codes? maximal-length sequences?
If EDAC is there its usually a checksum, which might be OK if the data is
not too important, but probably wont cut the mustard if you are transmitting
say a code upgrade, or a"let go" command to a crane.

I am interested to hear other peoples experiences with the converse -
analogue circuitry where digital is by far the best choice.

 

[The Real Andy]

"Terry Given" <the_domes@xtra.co.nz> wrote in message
news:KRJ6c.10303$rw6.202574@news.xtra.co.nz...

What is really surprising is the amount of times I see all-digital comms
links with no real error detection (and correction), often not even
parity.
The worst offenders use individual bit positions as control flags, thereby
ensuring that a bit-flip type of error will do the maximum harm. Have they
never heard of hamming distances? huffman codes? maximal-length sequences?
If EDAC is there its usually a checksum, which might be OK if the data is
not too important, but probably wont cut the mustard if you are
transmitting
say a code upgrade, or a"let go" command to a crane.

That is one of my pet-hates too. The worst place I see it done is in
industrial control and plc's - situated in probably one of the noisiest
environments.

PS. I never use flags in comms, always have an explicit instruction to
enable/disable each flag.

 

[The Real Andy]

"Ken Smith" <kensmith@violet.rahul.net> wrote in message
news:c3evim$7fq$1@blue.rahul.net...

In article <Xns94B1AF93F9A1Aohirohotmailcom@202.20.93.13>,
DaveC <bobason456@hotmail.com> wrote:
Some chips have separate Digital Grounds and Analog Grounds. Many data
sheets I've read simply say to ensure they are no more then a few
millivolts of each other. But can any one give me some advice on best
practice in regards to Shielding, PCB design, Power Sup issues? Or even
why
they are separate pins on the chip, if we are to simply tie them
together.

The basic ideas are:

The bypass capacitors should connect to the ground at or near the digital
ground so that large AC currents don't flow near the analog ground.

The op-amps etc should have their reference ground point brought to the
analog ground.

Idealy the analog ground and digital ground should only be interconnected
at the ADC chip so that no other currents flow in the analog ground.

To dispell some of the myth, check this out

http://www.analog.com/Analog_Root/static/pdf/dataConverters/MixedSignal_Sect10.pdf

I would love to hear others comments on this app note, In particular the
section 'Grounding in mixed signal systems'.

 

[Terry Given]

"The Real Andy" <i_luv_beer_especially_pilsners@yahoo.com.au> wrote in
message news:405b971d@dnews.tpgi.com.au...

"Terry Given" <the_domes@xtra.co.nz> wrote in message
news:KRJ6c.10303$rw6.202574@news.xtra.co.nz...

What is really surprising is the amount of times I see all-digital comms
links with no real error detection (and correction), often not even
parity.
The worst offenders use individual bit positions as control flags,
thereby
ensuring that a bit-flip type of error will do the maximum harm. Have
they
never heard of hamming distances? huffman codes? maximal-length
sequences?
If EDAC is there its usually a checksum, which might be OK if the data
is
not too important, but probably wont cut the mustard if you are
transmitting
say a code upgrade, or a"let go" command to a crane.

That is one of my pet-hates too. The worst place I see it done is in
industrial control and plc's - situated in probably one of the noisiest
environments.

PS. I never use flags in comms, always have an explicit instruction to
enable/disable each flag.

wise move. My background is AC motor control in industry - from << 1kW to >
1MW. sitting a control PCB 6 inches above a 1MW stack of power electronics,
with edge times of around 100ns forces you to learn all about robust design
practice *grin* (if not, BOOM)

weirdest thing I ever heard of? drives on a gantry crane in an aluminium
smelter (>> 50kA currents!!) had a problem when the gantry moved - all the
relays would open (or shut, depending on direction of movement) due to the
awesome no-longer-dc-when-you-move-with-respect-to-it magnetic field
present. Solution? open collector transistors....

stupidest thing wrt comms? a drongo who insists on using checksums not
CRC's, then "improving" his technique when sending code updates, by
transmitting every byte along with its complement (oh yes, doubling the
data, and for not much better protection). Funnily enough they still
sometimes download & execute garbled code, sometimes bad enough to require
manual intervention, which is a pain when the box is sealed to IP68 and sits
6m off the ground *sigh*

 

[Ken Smith]

In article <405b985d@dnews.tpgi.com.au>,
The Real Andy <i_luv_beer_especially_pilsners@yahoo.com.au> wrote:
[....]

To dispell some of the myth, check this out

http://www.analog.com/Analog_Root/static/pdf/dataConverters/MixedSignal_Sect10.pdf

There is quite a bit missing and some stuff wrong. I just lost my
connection twice will writing a big long discussion of it. I think I'll
go to bed now. Hopefully tomorrow the CPU gods will smile on me.

--
--
kensmith@rahul.net forging knowledge

 

[Mike]

On Fri, 19 Mar 2004 16:39:33 +0000 (UTC), Reg Edwards wrote:

"Mike" wrote> Don't ridicule the digital guys for not knowing what you know.
They don't
need to. They aren't playing in the same sandbox.

========================

Sorry Mike, no offence intended.

None taken... at least, not by me.

-- Mike --

 

[Ken Smith]

In article <c3gj44$m2m$1@blue.rahul.net>,
Ken Smith <kensmith@violet.rahul.net> wrote:

In article <405b985d@dnews.tpgi.com.au>,
The Real Andy <i_luv_beer_especially_pilsners@yahoo.com.au> wrote:
[....]
To dispell some of the myth, check this out

http://www.analog.com/Analog_Root/static/pdf/dataConverters/MixedSignal_Sect10.pdf

At 10.16, the document implies that surface mount decoupling capacitors
are better than through hole parts. In practice correctly installed
through hole capacitors with a 0.1" lead spacing can be better than
surface mount. The lead provides a very low impedance path from the
actual capacitance directly to the power and ground planes.

The placement of bypass capacitors always come down to a trade off. If a
surface mount logic chip has its Vcc connection run to a plain, you don't
want to do anything that forces the length of the Vcc connection to be
longer. This often forces the bypass capacitor back away to the far side
of the via. The length of the ground side trace on the bypass capacitor
is as important as the length of the Vcc side trace.

At 10.17 the advice about doing a two sided board is almost wrong. Since
you can't avoid holes in the plain on one side of the board, you really
want to also flood both sides of the board with ground. All signal and
power routing must take into consideration getting the low impedance
ground through the area.

At 10.18 they suggest that 30-40% of pins be used for ground without
talking about how they should be distributed. As far as RF signals are
concerned, if you ground 5 pins in a row, the middle pin does almost
nothing. You want to spread the gound pins down the length of the
connector.

They also suggest that multipoint grounding of the chassis is an OK thing
to do. In my experience, multipoint grounding always leads to trouble.
It increases both RF radiation and pick-up. If a circuit needs a shield,
that shield should be tied to the ground of the PCB and not to the chassis
of the system.

Near 10.26 they suggest that conncting AGND and DGND together at the ADC
is a bad idea because it leads to multiple connections between AGND and
DGND. This is only true if the inputs to the analog circuits cause the
AGND lines to be interconnected. In systems where this is not true, it is
often best to make the ground star near the ADC.

There is not enough attention payed to the running the DVcc connections.
Ideally, in a mother board, the DVcc should run over the DGND all the way
from the power supply connections to the point of use. The analog power
lines should run over the AGND, if there is one.

Near figure 10.34, they say that non-conductive ferrites are used in RF
beads. Beware, most of the ferrites used in beads that you would put on
power wiring are conductive. The beads are often coated in a
nonconductive material.

In the section on switching regulators, they can't seem to make up there
minds about where the input side capacitors on a switcher should be
placed. There should always be a bypass right at the controller chip.
The DC power should flow past the lead of the larger capacitor as it goes
from the input to the switching section. Any AC current that flows in the
input wire must have a matching current flowing in the ground connection.
As a result, you want the input side capacitor to provide a lower
impedance than the input wiring.

Output filtering is mensioned but input side filtering is not. An
inductor in the power input path can greatly reduce the conducted noise
from the switcher.

If the switcher is on the same PCB as the analog circuits, it is a good
idea to give the switcher its own local ground plain. The idea is to keep
the RF bottled up in the switcher area and not let it get out to the rest
of the circuit. The switcher's ground should hook to the main ground at a
single neck. The input and output power connections should run above this
neck to get from the switcher to the rest of the board. If input filter
inductor and output filter are used, a capacitor should be placed near the
neck above the main plain.


The suggest bypassing shown in Figure 10.45 is correct for a BGA package
but not for a TQFP. When you layout a TQFP, the traces that do not run
away on the top layer usually rund to vias under the body of the chip.
As a result, the power and ground connections of the chip are actually
under its body. Some of the bypass capacitors should be on the back of
the PCB to make the impedance between the Vcc and DGND low.

--
kensmith@rahul.net forging knowledge

--
--
kensmith@rahul.net forging knowledge

 

[Terry Given]

"Ken Smith" <kensmith@violet.rahul.net> wrote in message
news:c3i2ns$f50$1@blue.rahul.net...

In article <c3gj44$m2m$1@blue.rahul.net>,
Ken Smith <kensmith@violet.rahul.net> wrote:
In article <405b985d@dnews.tpgi.com.au>,
The Real Andy <i_luv_beer_especially_pilsners@yahoo.com.au> wrote:
[....]
To dispell some of the myth, check this out


http://www.analog.com/Analog_Root/static/pdf/dataConverters/MixedSignal_Se
ct10.pdf


At 10.16, the document implies that surface mount decoupling capacitors
are better than through hole parts. In practice correctly installed
through hole capacitors with a 0.1" lead spacing can be better than
surface mount. The lead provides a very low impedance path from the
actual capacitance directly to the power and ground planes.

I presume this is due to the via somehow? many leaded caps are actually smt
caps with leads attached to the metallised end caps. please elaborate....a
1mm long via with an 0.016" hole has about 1.2nH of inductance. By the time
this becomes important, skin effect ensures the solid component leg is no
better than a tube of wall thickness 66mm/sqrt(F Hz). so for 17um via
thickness, this corresponds to a frequency of 15MHz - smack bang in the
frequency where we are most interested in our bypass cap performance.

the biggest problem to overcome with leaded caps is their physical sixe.
trace the physical current loop....with an 0603 smt capacitor sitting 0.4mm
above the 0V plane (4-layer PCB) the physical loop can be no smaller than
(about) 1.5mm x 0.4mm. With a 2-layer pcb this becomes about 1.5mm x 1.6mm
(assume 1.6mm pcb thickness both cases). With a leaded caps, lead pitch 0.1"
= 2.5mm, the area WILL be bigger than that of an smt cap. Often leaded caps
have 0.1" leads bent out to 0.2" spacing, which forces the cap about 1mm
above the pcb, giving (4layer) a loop around 5mm x 1.4mm or 12x larger than
the 0603. Given that inductance is proportional to loop area, the 0.2"
leaded cap can be expected to have about 10x the inductance of the 0603 cap.

it is clear from the above discussion that traces etc. only make the problem
worse. keep them wide, and use multiple parallel vias. Likewise multiple smt
caps in parallel - heck AVX even make smt caps that are "rotated" 90
degrees, so the "endcaps" run along the longest axis of the caps, getting
the inductance even lower.

mind you, for large temperature excursions where differing TCEs can cause
mechanical failures, leaded parts can certainly be more robust

ref. "High Speed Digital Design, a handbook of black magic" H. Johnson & M.
Graham, Prentice Hall, ISBN 0-13-395724-1

The placement of bypass capacitors always come down to a trade off. If a
surface mount logic chip has its Vcc connection run to a plain, you don't
want to do anything that forces the length of the Vcc connection to be
longer. This often forces the bypass capacitor back away to the far side
of the via. The length of the ground side trace on the bypass capacitor
is as important as the length of the Vcc side trace.

yep, and manufacturing constraints often limit how close cap can be too (mfg
people dont like soldering a few bits on the underside of a pcb for some
reason....LOL)

At 10.17 the advice about doing a two sided board is almost wrong. Since
you can't avoid holes in the plain on one side of the board, you really
want to also flood both sides of the board with ground. All signal and
power routing must take into consideration getting the low impedance
ground through the area.

At 10.18 they suggest that 30-40% of pins be used for ground without
talking about how they should be distributed. As far as RF signals are
concerned, if you ground 5 pins in a row, the middle pin does almost
nothing. You want to spread the gound pins down the length of the
connector.

yep. Crazy the number of things you buy that are just plain wrong though -
Rabbit ethernet interface boards have a pair of connectors for bus, IO etc,
and (IIRC) only one 0V connection at all, even though the connectors are as
far apart as is physically possible.....absolutely guaranteeing that one
half of all the pins return current must flow through a loop that is as
large as the pcb *sigh*

They also suggest that multipoint grounding of the chassis is an OK thing
to do. In my experience, multipoint grounding always leads to trouble.
It increases both RF radiation and pick-up. If a circuit needs a shield,
that shield should be tied to the ground of the PCB and not to the chassis
of the system.

yep. Most shields tend to be electrostatic (ie capacitive) - doing it this
way makes sure the capacitive currents head straight back from whence they
came.

Near 10.26 they suggest that conncting AGND and DGND together at the ADC
is a bad idea because it leads to multiple connections between AGND and
DGND. This is only true if the inputs to the analog circuits cause the
AGND lines to be interconnected. In systems where this is not true, it is
often best to make the ground star near the ADC.

ROT should be used as guidelines, not followed slavishly (not a panacaea for
lack of understanding). If you understand WHY though......

There is not enough attention payed to the running the DVcc connections.
Ideally, in a mother board, the DVcc should run over the DGND all the way
from the power supply connections to the point of use. The analog power
lines should run over the AGND, if there is one.

yep. sometimes its not possible, but one should always try.

Near figure 10.34, they say that non-conductive ferrites are used in RF
beads. Beware, most of the ferrites used in beads that you would put on
power wiring are conductive. The beads are often coated in a
nonconductive material.

also, edges of toroids can be fairly sharp, and ferrite is HARD, so will
happily fret right through the epoxy coating given half a chance.....

In the section on switching regulators, they can't seem to make up there
minds about where the input side capacitors on a switcher should be
placed. There should always be a bypass right at the controller chip.
The DC power should flow past the lead of the larger capacitor as it goes
from the input to the switching section. Any AC current that flows in the
input wire must have a matching current flowing in the ground connection.
As a result, you want the input side capacitor to provide a lower
impedance than the input wiring.

well said.

Output filtering is mensioned but input side filtering is not. An
inductor in the power input path can greatly reduce the conducted noise
from the switcher.

yep. And what do the good books on smps EMI say? look at the spectrum of
those pretty trapezoidal current waveforms, it will tell you exactly how
your filter will behave. And when you design your filter, specifically
include all stray series L & shunt C......THEN analyse it. Remember, energy
you dont damp is energy you bounce around.

If the switcher is on the same PCB as the analog circuits, it is a good
idea to give the switcher its own local ground plain. The idea is to keep
the RF bottled up in the switcher area and not let it get out to the rest
of the circuit. The switcher's ground should hook to the main ground at a
single neck. The input and output power connections should run above this
neck to get from the switcher to the rest of the board. If input filter
inductor and output filter are used, a capacitor should be placed near the
neck above the main plain.

yep. Selective cuts in the 0V plane can help in this regard too, IF you know
what you are doing (clearly you do)

The suggest bypassing shown in Figure 10.45 is correct for a BGA package
but not for a TQFP. When you layout a TQFP, the traces that do not run
away on the top layer usually rund to vias under the body of the chip.
As a result, the power and ground connections of the chip are actually
under its body. Some of the bypass capacitors should be on the back of
the PCB to make the impedance between the Vcc and DGND low.

if your production manager doesnt hit you with a stick.

--
kensmith@rahul.net forging knowledge

Cheers
Terry