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Title: DFT Manager
Category: Senior Management
City: CA- Santa Clara
Salary: Open- Permanent
Job Description: Responsibilities
The DFT Manager requires to provide direction and expertise for the
evaluation, development and implementation of DFT solutions for current and
future designs. To improve testability, reduce test escapes, improve debug
capabilities, speed time to market and reduce test cost. Gain a clear
understanding of the design and defect density of the technology to
formulate the test/debug requirements and strategies for the design. To work
closely with EDA and ATE vendors. Provide turnkey solutions to test/debug
requirements by establishing DFT flow methodology that is easily integrated
into the existing design flow. Provide solutions for at-speed testing as
well as speed grading for current and future designs. Support product/test
team in pattern validation, design characterization efforts. Assist with
prototype debug and provide production support to identify yield
improvements.
Requirements
Must be knowledgeable on design and manufacturing issues impacting DPM
and methods to overcome them. Must also have a clear understanding of the
test/product engineering process in order to support their efforts. Must be
able to leverage/engage subcontractors and vendors to assure timely delivery
of milestones. Must have enough breadth to manage, motivate, and retain a
diverse talent pool.
Skills: Must have extensive hands-on experience in logic design flow:
micro-architecture, modeling, RTL implementation/verification, logic
synthesis, logic equivalent checking, static timing analysis, signal
integrity checks, and back-end support for timing closure. Must have a firm
understanding and hands-on experience on industry standard DFT techniques:
boundary scan (AC/DC), memory BIST and repair, logic BIST/pattern
compression, analog BIST, BIST for high-speed serial links, etc.
For more information on the current openings, please send us your resume in
Word format sighting the relevant job title to careers@negativelogic.com.
Category: Senior Management
City: CA- Santa Clara
Salary: Open- Permanent
Job Description: Responsibilities
The DFT Manager requires to provide direction and expertise for the
evaluation, development and implementation of DFT solutions for current and
future designs. To improve testability, reduce test escapes, improve debug
capabilities, speed time to market and reduce test cost. Gain a clear
understanding of the design and defect density of the technology to
formulate the test/debug requirements and strategies for the design. To work
closely with EDA and ATE vendors. Provide turnkey solutions to test/debug
requirements by establishing DFT flow methodology that is easily integrated
into the existing design flow. Provide solutions for at-speed testing as
well as speed grading for current and future designs. Support product/test
team in pattern validation, design characterization efforts. Assist with
prototype debug and provide production support to identify yield
improvements.
Requirements
Must be knowledgeable on design and manufacturing issues impacting DPM
and methods to overcome them. Must also have a clear understanding of the
test/product engineering process in order to support their efforts. Must be
able to leverage/engage subcontractors and vendors to assure timely delivery
of milestones. Must have enough breadth to manage, motivate, and retain a
diverse talent pool.
Skills: Must have extensive hands-on experience in logic design flow:
micro-architecture, modeling, RTL implementation/verification, logic
synthesis, logic equivalent checking, static timing analysis, signal
integrity checks, and back-end support for timing closure. Must have a firm
understanding and hands-on experience on industry standard DFT techniques:
boundary scan (AC/DC), memory BIST and repair, logic BIST/pattern
compression, analog BIST, BIST for high-speed serial links, etc.
For more information on the current openings, please send us your resume in
Word format sighting the relevant job title to careers@negativelogic.com.
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