Decoupling capacitors...

[Phil Hobbs]

On 12/10/20 7:22 PM, Clifford Heath wrote:

On 11/12/20 1:55 am, antispam@math.uni.wroc.pl wrote:
I wonder about wisdom of paralleling ceramic decoupling
capacitors.  I some old text I have found advice to
use 10uF (electrolytic), 100nF and 100pF in parallel.
Several relatively new text write about combinations
like 1uF and 100nF, both ceramic.

In case of electrolytic capacitors things seem clear:
electrolytic is mostly resitive in middle of frequency
boound and ceramic gives pure improvement.  However,
datasheets of modern ceramic capacitors suggest that
ESL is almost independent of capacitance (ESL groves
with size but in given size seem to vary only a little).
Simple RCL model shows that parallel ceramics will
have parallel resonace peak when capacitance differ
enough (about 3 times for modest peak, 10 times
gives substantial peak).  Parallel combination will
have smaller impedance above self resonant frequency
of smaller capacitor but the gain is modest.  OTOH
close to resonant peak we will have substantially
higher impedance.  For me it does not look like good
deal.  In fact, when low impendance at high
frequences is important it looks better to connect
several nominally identical capacitors.  With
usual tolerances they should give no parallel
resonace and lower impendace due to paralleling
of ESL.

In principle one could play tricks with resonance
frequencies putting parallel resonace at frequency
not present in circuit and serial resonances at
frequencies needing suppression.  But with usual
tolerances of ceramics this look impractical to me.

Anyway, I wonder if I missed something and paralleling
different decoupling ceramics gives some advantages?
Or is this advice about paralleling just repeating
old lore without understanding that world has
changed?

A colleague had all kinds of trouble with such paired capacitors
resonating around 900MHz in a specialised receiver for 144MHz. When you
get parasitic power plane oscillations far above the frequencies you\'re
expecting to see, it can be very mystifying.

CH.

That\'s not uncommon in badly-behaved SMPS parts--they generate a comb up
to, like, the 200th harmonic, and PCB trace resonances select a few of
them apparently at random. So you can have a 1.5 MHz switcher causing
125 MHz junk in one part of the circuit and 180 MHz junk in another.

Not so easy to debug if you haven\'t seen it before!

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

 

[Rick C]

On Thursday, December 10, 2020 at 6:58:56 PM UTC-5, Klaus Kragelund wrote:

10.12.20 17:33, jla...@highlandsniptechnology.com wrote:
On Thu, 10 Dec 2020 16:57:48 +0100, Jeroen Belleman
jer...@nospam.please> wrote:

On 2020-12-10 15:55, anti...@math.uni.wroc.pl wrote:
I wonder about wisdom of paralleling ceramic decoupling
capacitors. I some old text I have found advice to
use 10uF (electrolytic), 100nF and 100pF in parallel.
Several relatively new text write about combinations
like 1uF and 100nF, both ceramic.

In case of electrolytic capacitors things seem clear:
electrolytic is mostly resitive in middle of frequency
boound and ceramic gives pure improvement. However,
datasheets of modern ceramic capacitors suggest that
ESL is almost independent of capacitance (ESL groves
with size but in given size seem to vary only a little).
Simple RCL model shows that parallel ceramics will
have parallel resonace peak when capacitance differ
enough (about 3 times for modest peak, 10 times
gives substantial peak). Parallel combination will
have smaller impedance above self resonant frequency
of smaller capacitor but the gain is modest. OTOH
close to resonant peak we will have substantially
higher impedance. For me it does not look like good
deal. In fact, when low impendance at high
frequences is important it looks better to connect
several nominally identical capacitors. With
usual tolerances they should give no parallel
resonace and lower impendace due to paralleling
of ESL.

In principle one could play tricks with resonance
frequencies putting parallel resonace at frequency
not present in circuit and serial resonances at
frequencies needing suppression. But with usual
tolerances of ceramics this look impractical to me.

Anyway, I wonder if I missed something and paralleling
different decoupling ceramics gives some advantages?
Or is this advice about paralleling just repeating
old lore without understanding that world has
changed?



That looks roughly right, I didn\'t go into the details.
As a rule of thumb, I count 5nH ESL for a radially wired
capacitor with 2.5mm between the wires. It doesn\'t
really matter if it\'s ceramic or electrolytic, although
there may be unpleasant surprises sometimes. For
ceramic multi-layer SMD capacitors, it\'s about 0.5nH,
and it doesn\'t matter much if it\'s 1206, 0805 or even
smaller. It\'s the aspect ratio that counts.

There may be some virtue in combining an electrolytic
with an SMD ceramic, but paralleling multiple ceramic
SMDs of different values is basically nonsense. Small
electrolytics are useless for decoupling, because of
high ESR.

Jeroen Belleman

If you\'re designing fast stuff, use a multilayer board with a ground
plane and power planes or big pours. The fast low-impedance bypass is
the plane pours themselves. The ceramic caps just help out at mid
frequencies, and it doesn\'t much matter where they are.

Some loads, like CPUs, can have gross low-frequency current surges so
need a mot of microfarads somewhere. Polymers are good for that.

People like to draw graphs of ESR of various caps in parallel vs
frequency, and argue for a lot of different values. That\'s mostly
silly. The PCB planes are a great low-L, low-Q capacitor network.

I sometimes add SMA connectors to my board layouts, so I can TDR
traces and planes. That wrecks a lot of hand-wavey Black Magic theory.

I use 1 uF almost everywhere. Too many, actually.


I saw one board being assembled for Anritsu, in a shed in Hamamatsu.
It had 3000 bypass caps per board. Seems excessive.

There is some old Xilinx appnote that calls for hundreds of caps on
one FPGA. It was co-authored by CTS I think.


In a former employment, a large board with over 1000 caps had a production issue, so no caps was mounted. The board worked anyway due to the Stackup as Larkin explained

Lee Ritchie has a book where he travels into the details, \"right the first time\" I think it is called

Yeah, that\'s the guy who taught the class I took. He was very good and very thorough. Every significant point he made was done by explaining the theory, showing a simulation and then measurements on a board especially designed for the task. That\'s why I have confidence in the things he taught. He showed us the board with a cap mounted either next to the \"chip\", an inch from the chip or something like six inches from the chip. It made little difference how far away the cap was from the chip.... well, at six inches there was a small dip.

The point is the guy isn\'t just talking through his hat. I\'ve still got the books around here somewhere. Very good stuff.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Thursday, December 10, 2020 at 7:22:17 PM UTC-5, Clifford Heath wrote:

On 11/12/20 1:55 am, anti...@math.uni.wroc.pl wrote:
I wonder about wisdom of paralleling ceramic decoupling
capacitors. I some old text I have found advice to
use 10uF (electrolytic), 100nF and 100pF in parallel.
Several relatively new text write about combinations
like 1uF and 100nF, both ceramic.

In case of electrolytic capacitors things seem clear:
electrolytic is mostly resitive in middle of frequency
boound and ceramic gives pure improvement. However,
datasheets of modern ceramic capacitors suggest that
ESL is almost independent of capacitance (ESL groves
with size but in given size seem to vary only a little).
Simple RCL model shows that parallel ceramics will
have parallel resonace peak when capacitance differ
enough (about 3 times for modest peak, 10 times
gives substantial peak). Parallel combination will
have smaller impedance above self resonant frequency
of smaller capacitor but the gain is modest. OTOH
close to resonant peak we will have substantially
higher impedance. For me it does not look like good
deal. In fact, when low impendance at high
frequences is important it looks better to connect
several nominally identical capacitors. With
usual tolerances they should give no parallel
resonace and lower impendace due to paralleling
of ESL.

In principle one could play tricks with resonance
frequencies putting parallel resonace at frequency
not present in circuit and serial resonances at
frequencies needing suppression. But with usual
tolerances of ceramics this look impractical to me.

Anyway, I wonder if I missed something and paralleling
different decoupling ceramics gives some advantages?
Or is this advice about paralleling just repeating
old lore without understanding that world has
changed?
A colleague had all kinds of trouble with such paired capacitors
resonating around 900MHz in a specialised receiver for 144MHz. When you
get parasitic power plane oscillations far above the frequencies you\'re
expecting to see, it can be very mystifying.

CH.

When you have resonances at frequencies that high you should compare the wavelength to the board dimensions. 900 MHz ~ 1 foot I believe. Was the board a foot wide or maybe 6 inches? The resonances are as much between caps and the power planes as much as anything. The power planes have very low ESR and so will present rather sharp peaks if tuned with a low ESR inductance. The resonances between different caps are not so pronounced.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

[Clifford Heath]

On 11/12/20 2:56 pm, Rick C wrote:

On Thursday, December 10, 2020 at 7:22:17 PM UTC-5, Clifford Heath wrote:
On 11/12/20 1:55 am, anti...@math.uni.wroc.pl wrote:
I wonder about wisdom of paralleling ceramic decoupling
capacitors. I some old text I have found advice to
use 10uF (electrolytic), 100nF and 100pF in parallel.
Several relatively new text write about combinations
like 1uF and 100nF, both ceramic.

In case of electrolytic capacitors things seem clear:
electrolytic is mostly resitive in middle of frequency
boound and ceramic gives pure improvement. However,
datasheets of modern ceramic capacitors suggest that
ESL is almost independent of capacitance (ESL groves
with size but in given size seem to vary only a little).
Simple RCL model shows that parallel ceramics will
have parallel resonace peak when capacitance differ
enough (about 3 times for modest peak, 10 times
gives substantial peak). Parallel combination will
have smaller impedance above self resonant frequency
of smaller capacitor but the gain is modest. OTOH
close to resonant peak we will have substantially
higher impedance. For me it does not look like good
deal. In fact, when low impendance at high
frequences is important it looks better to connect
several nominally identical capacitors. With
usual tolerances they should give no parallel
resonace and lower impendace due to paralleling
of ESL.

In principle one could play tricks with resonance
frequencies putting parallel resonace at frequency
not present in circuit and serial resonances at
frequencies needing suppression. But with usual
tolerances of ceramics this look impractical to me.

Anyway, I wonder if I missed something and paralleling
different decoupling ceramics gives some advantages?
Or is this advice about paralleling just repeating
old lore without understanding that world has
changed?
A colleague had all kinds of trouble with such paired capacitors
resonating around 900MHz in a specialised receiver for 144MHz. When you
get parasitic power plane oscillations far above the frequencies you\'re
expecting to see, it can be very mystifying.

CH.

When you have resonances at frequencies that high you should compare the wavelength to the board dimensions. 900 MHz ~ 1 foot I believe. Was the board a foot wide or maybe 6 inches?

No, the two 0603 caps were directly adjacent across the same two traces.
After diagnosing the problem it turned out to be the ESL of the larger
cap resonating with the smaller one.

CH

 

[bilou]

On 10/12/2020 15:55, antispam@math.uni.wroc.pl wrote:

I wonder about wisdom of paralleling ceramic decoupling
capacitors. I some old text I have found advice to
use 10uF (electrolytic), 100nF and 100pF in parallel.
Several relatively new text write about combinations
like 1uF and 100nF, both ceramic.

In case of electrolytic capacitors things seem clear:
electrolytic is mostly resitive in middle of frequency
boound and ceramic gives pure improvement. However,
datasheets of modern ceramic capacitors suggest that
ESL is almost independent of capacitance (ESL groves
with size but in given size seem to vary only a little).
Simple RCL model shows that parallel ceramics will
have parallel resonace peak when capacitance differ
enough (about 3 times for modest peak, 10 times
gives substantial peak). Parallel combination will
have smaller impedance above self resonant frequency
of smaller capacitor but the gain is modest. OTOH
close to resonant peak we will have substantially
higher impedance. For me it does not look like good
deal. In fact, when low impendance at high
frequences is important it looks better to connect
several nominally identical capacitors. With
usual tolerances they should give no parallel
resonace and lower impendace due to paralleling
of ESL.

In principle one could play tricks with resonance
frequencies putting parallel resonace at frequency
not present in circuit and serial resonances at
frequencies needing suppression. But with usual
tolerances of ceramics this look impractical to me.

Anyway, I wonder if I missed something and paralleling
different decoupling ceramics gives some advantages?
Or is this advice about paralleling just repeating
old lore without understanding that world has
changed?

There is a very simple rule about decoupling capacitors:
Too many is always good
Too few can lead to nightmares.

Examples :

Long time ago I noticed that when removing battery
from a TV remote it was still able to send about 10
commands with no battery at all.
When missing adding as big as possible capacitor (about 1000µF)
in parallel with it increased the life of the battery by
a few years.

In a tube UHF amplifier the final stage had is 2KV anode
supply decoupled by the classical mica sheet plus a 1000pF
ceramic.
HV supply came from a 2m long lead.
When using this final stage for television I noticed
some very bad echoes on the picture.
It took me sometime to find that the cause was radiation
at video frequencies from the 2m lead picked by the vidicon camera.
A hard to find 2KV 0.1µF capacitor solved the problem.

At UHF frequencies a nice trick is to use open ended quarter wavelength
coaxial cable as decoupling capacitors.

 

[Jeroen Belleman]

Cursitor Doom wrote:

On Thu, 10 Dec 2020 16:25:45 +0100, Gerhard Hoffmann <dk4xp@arcor.de
wrote:

Am 10.12.20 um 15:55 schrieb antispam@math.uni.wroc.pl:
I wonder about wisdom of paralleling ceramic decoupling
capacitors. I some old text I have found advice to
use 10uF (electrolytic), 100nF and 100pF in parallel.
Several relatively new text write about combinations
like 1uF and 100nF, both ceramic.

http://www.hoffmann-hochfrequenz.de/downloads/experiments_with_decoupling_capacitors.pdf


cheers, Gerhard

Gerhard, I think you\'ll find it\'s easier to read the exact
self-resonant frequency of the cap by putting your VNA in phase mode
and placing your marker(s) on the cross-over point.

Why should that matter? We\'re talking decoupling, not
tuned circuits.

Jeroen Belleman

 

[Jeroen Belleman]

Cursitor Doom wrote:

On Thu, 10 Dec 2020 16:25:45 +0100, Gerhard Hoffmann <dk4xp@arcor.de
wrote:

Am 10.12.20 um 15:55 schrieb antispam@math.uni.wroc.pl:
I wonder about wisdom of paralleling ceramic decoupling
capacitors. I some old text I have found advice to
use 10uF (electrolytic), 100nF and 100pF in parallel.
Several relatively new text write about combinations
like 1uF and 100nF, both ceramic.

http://www.hoffmann-hochfrequenz.de/downloads/experiments_with_decoupling_capacitors.pdf


cheers, Gerhard

Gerhard, I think you\'ll find it\'s easier to read the exact
self-resonant frequency of the cap by putting your VNA in phase mode
and placing your marker(s) on the cross-over point.

Why should that matter? We\'re talking decoupling, not
tuned circuits.

Jeroen Belleman

 

[Jasen Betts]

On 2020-12-10, Cursitor Doom <cd@noreply.com> wrote:

On Thu, 10 Dec 2020 16:25:45 +0100, Gerhard Hoffmann <dk4xp@arcor.de
wrote:

Am 10.12.20 um 15:55 schrieb antispam@math.uni.wroc.pl:
I wonder about wisdom of paralleling ceramic decoupling
capacitors. I some old text I have found advice to
use 10uF (electrolytic), 100nF and 100pF in parallel.
Several relatively new text write about combinations
like 1uF and 100nF, both ceramic.


http://www.hoffmann-hochfrequenz.de/downloads/experiments_with_decoupling_capacitors.pdf


cheers, Gerhard

From your site:

\"The 60 mm of wire make quite a mess. Now think if you trust C
measurements on those multimeters with unknown frequency and long
cables.\"


We seem to have gone backwards. 40 years ago I bought a multimeter
with LCR from Maplins or Conrad; can\'t recall which one (so hardly a
specialist supplier!) and it had a very useful square centimeter of
breadboard at the top just for directly plugging in caps and coils. I
haven\'t seen one since in all those 40 years.

They are different now.

https://www.aliexpress.com/item/32728109491.html

--
Jasen.

 

[Uwe Bonnes]

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

fredag den 11. december 2020 kl. 00.02.16 UTC+1 skrev Uwe Bonnes:
anti...@math.uni.wroc.pl wrote:
...
Anyway, I wonder if I missed something and paralleling
different decoupling ceramics gives some advantages?
Or is this advice about paralleling just repeating
old lore without understanding that world has
changed?

If you want broad range loew impedance, consider feedthrough
capacitors like Murata NFM(21PS).

you can also get capacitor that are \"rotated\" so they short and wide
i.e. 0306 instead of 0603

Look at the Murata impedance diagrams. Rotated is better, but NFM is
much better.
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 1623569 ------- Fax. 06151 1623305 ---------

 

[Gerhard Hoffmann]

Am 11.12.20 um 11:47 schrieb Uwe Bonnes:

Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

If you want broad range loew impedance, consider feedthrough
capacitors like Murata NFM(21PS).

you can also get capacitor that are \"rotated\" so they short and wide
i.e. 0306 instead of 0603

Look at the Murata impedance diagrams. Rotated is better, but NFM is
much better.

In 2012 I have bought some 0612, but the bag is still unopened.
Their C*V product / area is worse than for 1206 DK 446-4072-1-nd

I found x2y capacitors more interesting, like DK 311-1246-1-ND
originally Johanson, IIRC. They provoke a layout with more vias close
together, so part of the currents in the vias cancel.
Also never tested, I could not get them space-qualified.

Cheers, Gerhard

 

[Gerhard Hoffmann]

Am 11.12.20 um 00:42 schrieb Cursitor Doom:

\"The 60 mm of wire make quite a mess. Now think if you trust C
measurements on those multimeters with unknown frequency and long
cables.\"


We seem to have gone backwards. 40 years ago I bought a multimeter
with LCR from Maplins or Conrad; can\'t recall which one (so hardly a
specialist supplier!) and it had a very useful square centimeter of
breadboard at the top just for directly plugging in caps and coils. I
haven\'t seen one since in all those 40 years.

What can be more backwards than a HP 4274A bridge? Probably more
than 40 years, and you can connect the capacitors correctly, instead
of using the harmless looking Hirschmann pliers.

BTW it is still quite accurate in spite of the age. I have an equally
old Siemens Styrofoil capacitor, 47000 pF nominal, and it is measured
as 47003 pF. On a hot summer day, would you offer.., oh sorry,
it would probably just fit.

I had once an exploded electrolytic in it and replaced most of
the candidates. I carefully kept away from the bridge circuits,
there are zillions of things to adjust.

Cheers, Gerhard

 

[Uwe Bonnes]

Gerhard Hoffmann <dk4xp@arcor.de> wrote:

Am 11.12.20 um 11:47 schrieb Uwe Bonnes:
Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

If you want broad range loew impedance, consider feedthrough
capacitors like Murata NFM(21PS).

you can also get capacitor that are \"rotated\" so they short and wide
i.e. 0306 instead of 0603


Look at the Murata impedance diagrams. Rotated is better, but NFM is
much better.

In 2012 I have bought some 0612, but the bag is still unopened.
Their C*V product / area is worse than for 1206 DK 446-4072-1-nd

For C*V you can have bulky ceramic some more distance away.

I found x2y capacitors more interesting, like DK 311-1246-1-ND
originally Johanson, IIRC. They provoke a layout with more vias close
together, so part of the currents in the vias cancel.

Yes, NFM is Muratas x2y. That is what I am taking about.

Bye
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 1623569 ------- Fax. 06151 1623305 ---------

 

[Rick C]

On Friday, December 11, 2020 at 1:13:11 AM UTC-5, Clifford Heath wrote:

On 11/12/20 2:56 pm, Rick C wrote:
On Thursday, December 10, 2020 at 7:22:17 PM UTC-5, Clifford Heath wrote:
On 11/12/20 1:55 am, anti...@math.uni.wroc.pl wrote:
I wonder about wisdom of paralleling ceramic decoupling
capacitors. I some old text I have found advice to
use 10uF (electrolytic), 100nF and 100pF in parallel.
Several relatively new text write about combinations
like 1uF and 100nF, both ceramic.

In case of electrolytic capacitors things seem clear:
electrolytic is mostly resitive in middle of frequency
boound and ceramic gives pure improvement. However,
datasheets of modern ceramic capacitors suggest that
ESL is almost independent of capacitance (ESL groves
with size but in given size seem to vary only a little).
Simple RCL model shows that parallel ceramics will
have parallel resonace peak when capacitance differ
enough (about 3 times for modest peak, 10 times
gives substantial peak). Parallel combination will
have smaller impedance above self resonant frequency
of smaller capacitor but the gain is modest. OTOH
close to resonant peak we will have substantially
higher impedance. For me it does not look like good
deal. In fact, when low impendance at high
frequences is important it looks better to connect
several nominally identical capacitors. With
usual tolerances they should give no parallel
resonace and lower impendace due to paralleling
of ESL.

In principle one could play tricks with resonance
frequencies putting parallel resonace at frequency
not present in circuit and serial resonances at
frequencies needing suppression. But with usual
tolerances of ceramics this look impractical to me.

Anyway, I wonder if I missed something and paralleling
different decoupling ceramics gives some advantages?
Or is this advice about paralleling just repeating
old lore without understanding that world has
changed?
A colleague had all kinds of trouble with such paired capacitors
resonating around 900MHz in a specialised receiver for 144MHz. When you
get parasitic power plane oscillations far above the frequencies you\'re
expecting to see, it can be very mystifying.

CH.

When you have resonances at frequencies that high you should compare the wavelength to the board dimensions. 900 MHz ~ 1 foot I believe. Was the board a foot wide or maybe 6 inches?
No, the two 0603 caps were directly adjacent across the same two traces.
After diagnosing the problem it turned out to be the ESL of the larger
cap resonating with the smaller one.

Traces??? What do you mean traces? What sort of board in 2020 doesn\'t have power/ground planes? Oh, was this a board designed in 1999?

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

 

[Cursitor Doom]

On Thu, 10 Dec 2020 16:52:19 -0800, jlarkin@highlandsniptechnology.com
wrote:

I don\'t think I have ever used too few bypass caps. Always too many.

I know one guy who didn\'t use bypass caps on digital boards, and his
stuff worked.

So was he

a) stupid
b) a genius
c) just lucky

A lot of big digital ICs have on-chip supply bypass caps. I measured
an FPGA that had several, the biggest being a few hundred nF. That
takes care of the high-frequency stuff.

What exactly do you mean by \"on-chip\" in this context?

 

[Cursitor Doom]

On Fri, 11 Dec 2020 08:46:49 -0000 (UTC), Jasen Betts
<usenet@revmaps.no-ip.org> wrote:

They are different now.

https://www.aliexpress.com/item/32728109491.html

Hmmm. There was once a time when I would dismiss these things out of
hand, but I have to confess I\'ve had to revise my opinions of the
cheap Chinese gadgets of late. In fact I think I might go on a buying
splurge of all these kind of devices just in case there are
retaliationary measures afoot to punish China over its refusal to
allow international investigators access to the Whuhan lab and fish
market. The obvious soft target for such retaliation is to place huge
tariffs on direct imports of Chinese goods.

 

[Cursitor Doom]

On Fri, 11 Dec 2020 08:46:49 -0000 (UTC), Jasen Betts
<usenet@revmaps.no-ip.org> wrote:

On 2020-12-10, Cursitor Doom <cd@noreply.com> wrote:

We seem to have gone backwards. 40 years ago I bought a multimeter
with LCR from Maplins or Conrad; can\'t recall which one (so hardly a
specialist supplier!) and it had a very useful square centimeter of
breadboard at the top just for directly plugging in caps and coils. I
haven\'t seen one since in all those 40 years.

They are different now.

https://www.aliexpress.com/item/32728109491.html

THIS looks interesting, if the specs are to be believed:

https://tinyurl.com/y42fgm2r

Think I might just take a punt on it....

 

[Rick C]

On Friday, December 11, 2020 at 7:54:11 PM UTC-5, Cursitor Doom wrote:

On Thu, 10 Dec 2020 16:52:19 -0800, jla...@highlandsniptechnology.com
wrote:
I don\'t think I have ever used too few bypass caps. Always too many.

I know one guy who didn\'t use bypass caps on digital boards, and his
stuff worked.
So was he

a) stupid
b) a genius
c) just lucky
A lot of big digital ICs have on-chip supply bypass caps. I measured
an FPGA that had several, the biggest being a few hundred nF. That
takes care of the high-frequency stuff.
What exactly do you mean by \"on-chip\" in this context?

Ceramic caps in the package, not in silicon. In the course I took Lee Ritchey was explaining ground bounce and I asked him if \"in package\" decoupling caps help ground bounce. He had to think about it seriously for a bit. Then he said no. I think he is wrong. By decoupling power to ground the ground current surge is split between the power pins and the ground pins and so the voltage is cut, perhaps as much as in half. In addition, any pins changing in the opposite direction subtract from the net current surge and so the voltage spike is further reduced.

Of course that only occurred to me years later when I was idly thinking about it. lol That\'s the sort of stuff that you can see clearly when you are not trying.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

 

[John Larkin]

On Sat, 12 Dec 2020 00:54:00 +0000, Cursitor Doom <cd@noreply.com>
wrote:

On Thu, 10 Dec 2020 16:52:19 -0800, jlarkin@highlandsniptechnology.com
wrote:

I don\'t think I have ever used too few bypass caps. Always too many.

I know one guy who didn\'t use bypass caps on digital boards, and his
stuff worked.

So was he

a) stupid
b) a genius
c) just lucky

His stuff worked, and he knew what he was doing.

A lot of big digital ICs have on-chip supply bypass caps. I measured
an FPGA that had several, the biggest being a few hundred nF. That
takes care of the high-frequency stuff.

What exactly do you mean by \"on-chip\" in this context?

I think the caps are monolithic on the chip, on the core and the bank
supplies. The Xilinx BGA package is pretty thin and has no obvious
bumps. I suppose a few tiny ceramics inside are possible. Our Xray
doesn\'t have much resolution, but I might try. It\'s mainly a
parts-on-reels counter.

Anyhow, knowing about the internal caps means I don\'t need many bypass
caps on the board, and none need to be especially close to the ZYNQ.

 

[Clifford Heath]

On 12/12/20 2:59 am, Rick C wrote:

On Friday, December 11, 2020 at 1:13:11 AM UTC-5, Clifford Heath wrote:
On 11/12/20 2:56 pm, Rick C wrote:
On Thursday, December 10, 2020 at 7:22:17 PM UTC-5, Clifford Heath wrote:
On 11/12/20 1:55 am, anti...@math.uni.wroc.pl wrote:
I wonder about wisdom of paralleling ceramic decoupling
capacitors. I some old text I have found advice to
use 10uF (electrolytic), 100nF and 100pF in parallel.
Several relatively new text write about combinations
like 1uF and 100nF, both ceramic.

In case of electrolytic capacitors things seem clear:
electrolytic is mostly resitive in middle of frequency
boound and ceramic gives pure improvement. However,
datasheets of modern ceramic capacitors suggest that
ESL is almost independent of capacitance (ESL groves
with size but in given size seem to vary only a little).
Simple RCL model shows that parallel ceramics will
have parallel resonace peak when capacitance differ
enough (about 3 times for modest peak, 10 times
gives substantial peak). Parallel combination will
have smaller impedance above self resonant frequency
of smaller capacitor but the gain is modest. OTOH
close to resonant peak we will have substantially
higher impedance. For me it does not look like good
deal. In fact, when low impendance at high
frequences is important it looks better to connect
several nominally identical capacitors. With
usual tolerances they should give no parallel
resonace and lower impendace due to paralleling
of ESL.

In principle one could play tricks with resonance
frequencies putting parallel resonace at frequency
not present in circuit and serial resonances at
frequencies needing suppression. But with usual
tolerances of ceramics this look impractical to me.

Anyway, I wonder if I missed something and paralleling
different decoupling ceramics gives some advantages?
Or is this advice about paralleling just repeating
old lore without understanding that world has
changed?
A colleague had all kinds of trouble with such paired capacitors
resonating around 900MHz in a specialised receiver for 144MHz. When you
get parasitic power plane oscillations far above the frequencies you\'re
expecting to see, it can be very mystifying.

CH.

When you have resonances at frequencies that high you should compare the wavelength to the board dimensions. 900 MHz ~ 1 foot I believe. Was the board a foot wide or maybe 6 inches?
No, the two 0603 caps were directly adjacent across the same two traces.
After diagnosing the problem it turned out to be the ESL of the larger
cap resonating with the smaller one.

Traces??? What do you mean traces? What sort of board in 2020 doesn\'t have power/ground planes? Oh, was this a board designed in 1999?

I haven\'t seen the layout or know what part of the circuit it was for.
Yes, it probably has power/ground, but its common to branch off and add
extra filtering to the first RF stages, for example. But you don\'t do
RF, so you wouldn\'t have much experience at that.

 

[Jim MacArthur]

Most of my parallel cap woes have involved LDO output caps. Some LDOs are _really_ sensitive to the ESR, which can get hard to figure out when you\'ve got a lot of caps of various sizes in various positions. You\'ll think you\'ve done it right, stress-tested your design, then the purchasing engineer changes cap brands and the vreg starts to oscillate.