creating program

[aadi]

i have learned every aspect of VHDL but i still can't exersise it to make complex program.
i need a code for data encryption standard and also for key generation. but i can't get a single way to do so
plzz help me

 

[KJ]

On Friday, October 16, 2015 at 5:36:53 AM UTC-4, aadi wrote:

i have learned every aspect of VHDL but i still can't exersise it to make complex program.
i need a code for data encryption standard and also for key generation. but i can't get a single way to do so
plzz help me

Stating what you say you 'need' and not showing what you've 'done' doesn't typically motivate anybody to help.

Some suggestions:
- Post some code for people to review and comment
- Pay somebody to write the code for you
- English may not be your first language, but 'plzz' is not even close to 'please'...it's closer to 'pizza'. Showing some bit of professionalism is often useful

Kevin

 

[Thomas Stanka]

Am Freitag, 16. Oktober 2015 11:36:53 UTC+2 schrieb aadi:

i have learned every aspect of VHDL but i still can't exersise it to make complex program.
i need a code for data encryption standard and also for key generation. but i can't get a single way to do so
plzz help me

In general, it is agreed that writing a "Program" requires you to have Software and Compiler that generates a Program out of your Software.

VHDL is mainly a hardware description language, I know no Compiler allowing you to generate a executeable out of VHDL, instead you will find several Simulators, that allow you to simulate the Code you wrote.

If you have learned every aspect of VHDL this is nothing new for you, so your problem should be with the data encryption, not with HDL descripton itself, so you might ask in a group dealing with encyption standard.

A VHDL code for DES can easily take some man-month work force. If you need easy way register by open cores and download the DES core from there.

In this group you should provide specific questions in order to receive specific answers.

regards Thomas

 

[glen herrmannsfeldt]

aadi <aanchalgurawa@gmail.com> wrote:

i have learned every aspect of VHDL but i still can't exersise it
to make complex program.

I started VHDL, and though I have never written a 'program' in it, I
have designed some fairly complicated logic that actually works.

I won't claim to undestand even half of VHDL, as they are adding to it
faster than I can learn, and faster than the systems I use it with
can keep up.

(I had some years of verilog before, but only learned a small fraction
of VHDL before I knew enough to start writing it.)

i need a code for data encryption standard and also for key generation.
but i can't get a single way to do so

Do remember that VHDL is not a software programming language.

-- glen

 

On Friday, October 16, 2015 at 12:36:53 PM UTC+3, aadi wrote:

i have learned every aspect of VHDL but i still can't exersise it to make complex program.
i need a code for data encryption standard and also for key generation. but i can't get a single way to do so
plzz help me

You may want to see some examples. A simple UART project
http://bknpk.ddns.net/my_web/MiscellaneousHW/UART/uart_tx_1.html
A more complex design based on some free open IP stack. It also synthesized with Xilinx free XST and simulated with post NGD net-list.
All is done with the free VHDL simulator GHDL
http://bknpk.ddns.net/my_web/IP_STACK/start_1.html

 

[aadi]

Thanks Kevin for your comment.
Well here is my code its running only for one round but my mentor told me to change it into a behavioural code and not to use for loop.


key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 10 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 11 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 12 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 13 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 14 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 15 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(27) & key_l(0 to 26);
key_r(0 to 27) <= key_r(27) & key_r(0 to 26);
else
key_l(0 to 27) <= key_l(1 to 27) & key_l(0);
key_r(0 to 27) <= key_r(1 to 27) & key_r(0);
end if;
when others =>
end case;
end if;

end process Key;

cntrl: process (clk, dirtn)
variable count : integer range 0 to 15:=0;
begin

if (rising_edge(clk) and clk='1') then
if decipher = '0' then
if (dirtn='1') then
count:= count+ 1;
counter<=count;
else
if decipher = '1' then
count:= count- 1;
counter<=count;
end if;
end if;
end if;
end if;
end process cntrl;
end behavioural;

 

[Igmar Palsenberg]

Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi:
> i have learned every aspect of VHDL but i still can't exersise it to make complex program.

It's VHDL, not C or Java. VHDL is a description, not a program.

> i need a code for data encryption standard and also for key generation. but i can't get a single way to do so

What is the question ? The're plenty of open sources VHDL examples available, lots of them on opencores.


Igmar

 

[rickman]

On 10/28/2015 8:06 AM, Igmar Palsenberg wrote:

Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi:
i have learned every aspect of VHDL but i still can't exersise it to make complex program.

It's VHDL, not C or Java. VHDL is a description, not a program.

That's not very fair. VHDL is used to describe hardware, but it is a
perfectly good programming language too. That is how we use it for test
benches.

i need a code for data encryption standard and also for key generation. but i can't get a single way to do so

What is the question ? The're plenty of open sources VHDL examples available, lots of them on opencores.


Igmar

--

Rick

 

[glen herrmannsfeldt]

rickman <gnuarm@gmail.com> wrote:
> On 10/28/2015 8:06 AM, Igmar Palsenberg wrote:

(snip on VHDL and programs)

It's VHDL, not C or Java. VHDL is a description, not a program.

That's not very fair. VHDL is used to describe hardware, but it is a
perfectly good programming language too. That is how we use it for test
benches.

I think I also don't like the use of the word 'program' even in
the case of test benches.

To me, program has too much implication of sequential execution
(even in the case of parallel programming) that I think some other
word should be used.

I might use design, which I think works in the case of hardware
and test benches, which both need to be designed, if not described.

Though test benches could also be described, even if they aren't
hardware.

(But the idea of a test bench comes from the days when they were
hardware, even furniture.)

-- glen

 

[Igmar Palsenberg]

Op woensdag 28 oktober 2015 17:29:38 UTC+1 schreef rickman:

On 10/28/2015 8:06 AM, Igmar Palsenberg wrote:
Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi:
i have learned every aspect of VHDL but i still can't exersise it to make complex program.

It's VHDL, not C or Java. VHDL is a description, not a program.

That's not very fair. VHDL is used to describe hardware, but it is a
perfectly good programming language too. That is how we use it for test
benches.

That's not it's primary goal. That the language allows it, sure, but that doesn't mean it's build for that. Doing C or VHDL requires a totally different mindset.


Igmar

 

[rickman]

On 10/31/2015 9:16 AM, Igmar Palsenberg wrote:

Op woensdag 28 oktober 2015 17:29:38 UTC+1 schreef rickman:
On 10/28/2015 8:06 AM, Igmar Palsenberg wrote:
Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi:
i have learned every aspect of VHDL but i still can't exersise it to make complex program.

It's VHDL, not C or Java. VHDL is a description, not a program.

That's not very fair. VHDL is used to describe hardware, but it is a
perfectly good programming language too. That is how we use it for test
benches.

That's not it's primary goal. That the language allows it, sure, but that doesn't mean it's build for that. Doing C or VHDL requires a totally different mindset.

I think your distinction is pointless. You said "VHDL is a description,
not a program" and I have you an example when this is not true. End of
discussion for me.

As to the "mindset", there was a software designer who wanted to code an
FPGA in VHDL and came here asking for advice. We told him about how he
needed to adjust his thinking to design hardware and not code software.
I wrote to him personally to explain why this was important and came
close to getting some consulting time with his firm. In the end his
bosses had faith that he could do a good job and so he wrote the code
himself, without any trouble.

I learned that although I was a hardware person who was able to more
easily think about the hardware I was designing as gates and register,
this is *not* required, rather you *can* write VHDL as a sequential
language as long as you understand the various processes were all in
parallel. Parallel processes are not unique to hardware.

The really funny part was that the guy talked his bosses into sending me
a small check for the time I spent helping him while I insisted that was
just the cost of marketing for me and it was not needed. Not very often
I tell customers to *not* pay me. Lol

--

Rick

 

[rickman]

On 10/28/2015 6:39 PM, glen herrmannsfeldt wrote:

rickman <gnuarm@gmail.com> wrote:
On 10/28/2015 8:06 AM, Igmar Palsenberg wrote:

(snip on VHDL and programs)

It's VHDL, not C or Java. VHDL is a description, not a program.

That's not very fair. VHDL is used to describe hardware, but it is a
perfectly good programming language too. That is how we use it for test
benches.

I think I also don't like the use of the word 'program' even in
the case of test benches.

To me, program has too much implication of sequential execution
(even in the case of parallel programming) that I think some other
word should be used.

I might use design, which I think works in the case of hardware
and test benches, which both need to be designed, if not described.

Though test benches could also be described, even if they aren't
hardware.

(But the idea of a test bench comes from the days when they were
hardware, even furniture.)

I just call it "code".

--

Rick

 

[Andy]

Any coder worth his salt must know his/her compiler, be it C or VHDL. For HDLs, that typically means we need to know 2 different compilers (simulator and synthesis tools).

Even in purely sequential languages, the best compilers optimize the object code for the processor's inherent parallel execution capabilities based on dependencies, the same as a VHDL synthesis tool does for sequential code in processes and subprograms.

I agree that there are times (e.g. synchronization boundaries) where we need to code very close to the HW we need.

But at other times, coding for behavior (think throughput and clock cycles of latency) rather than HW (think gates and registers), solves more problems (will the HW behave the way we want?)

Otherwise, we leave 90% of the synthesis tool's capability on the table (we do its job for it by darn near coding a netlist).

Andy

 

Am Freitag, 23. Oktober 2015 09:48:40 UTC+2 schrieb aadi:

Thanks Kevin for your comment.
Well here is my code its running only for one round but my mentor told me to change it into a behavioural code and not to use for loop.


key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 10 =
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 11 =
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 12 =
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 13 =
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 14 =
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 15 =
if (decipher = '1') then
key_l(0 to 27) <= key_l(27) & key_l(0 to 26);
key_r(0 to 27) <= key_r(27) & key_r(0 to 26);
else
key_l(0 to 27) <= key_l(1 to 27) & key_l(0);
key_r(0 to 27) <= key_r(1 to 27) & key_r(0);
end if;
when others =
end case;
end if;

end process Key;

cntrl: process (clk, dirtn)
variable count : integer range 0 to 15:=0;
begin

if (rising_edge(clk) and clk='1') then
if decipher = '0' then
if (dirtn='1') then
count:= count+ 1;
counter<=count;
else
if decipher = '1' then
count:= count- 1;
counter<=count;
end if;
end if;
end if;
end if;
end process cntrl;
end behavioural;

Hi,
just some hint for the case selection:
If you have a number of when branches with identical statements you can combine them into one branch:

e.g.:
when 10 to 14 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;

Nonsequential selection values can be grouped using an or symbol:

like this:
when 2 | 5 | 17 => -- do something

look here for more details: http://vhdl.renerta.com/mobile/source/vhd00014.htm

Have a nice synthesis
Eilert

 

[Andy]

Excellent suggestion.

You can define an integer subtype with the appropriate range (and a descriptive name) to use in the choice expression, or to select a slice of an array.

I use an "_range" suffix on such subtype names.

subtype active_range is integer range 10 to 14;
....
when active_range =>
....

"downto" direction also works for case choice expressions. It must match the array index direction when used to index an array.

subtype status_range is integer range 7 downto 0;
....
status := data_word(status_range);
....

You can also use such a subtype in a loop indexing scheme:

for i in status_range loop
....

Andy

 

On Sunday, November 1, 2015 at 8:27:30 AM UTC+1, rickman wrote:

I think your distinction is pointless. You said "VHDL is a description,
not a program" and I have you an example when this is not true. End of
discussion for me.

Fine. That doesn't mean you're right.

As to the "mindset", there was a software designer who wanted to code an
FPGA in VHDL and came here asking for advice. We told him about how he
needed to adjust his thinking to design hardware and not code software.
I wrote to him personally to explain why this was important and came
close to getting some consulting time with his firm. In the end his
bosses had faith that he could do a good job and so he wrote the code
himself, without any trouble.

It's a whole different thing, assuming the end result ends up on a FPGA. Software is sequenced, around datastructures. VHDL is not sequenced, and doesn't have thing software has : Lock issues, memory alignment issues, etc.

With software, you attach a debugger, and you can step through. With VHDL, it's not that simple. So yes, I call this a different mindset. If you think like a software programmer, you'll sooner or later end up with a non-working, hard to debug prototype.

I learned that although I was a hardware person who was able to more
easily think about the hardware I was designing as gates and register,
this is *not* required, rather you *can* write VHDL as a sequential
language as long as you understand the various processes were all in
parallel. Parallel processes are not unique to hardware.

I doubt that still works for a *very* large design. On software, the OS handes a lot for you. No cache flushes, no memory barriers, etc.

Can a programmer while VHDL code ? Sure. But there is a huge different between good and "it works". Every monkey can write PHP code, but writing good, maintainable code is a different story.


Igmar

 

[Andy]

On Monday, November 9, 2015 at 5:50:51 AM UTC-6, igmar.pa...@boostermedia.com wrote:

It's a whole different thing, assuming the end result ends up on a FPGA. Software is sequenced, around datastructures. VHDL is not sequenced, and doesn't have thing software has : Lock issues, memory alignment issues, etc.

Really? You think a modern SW compiler doesn't tweak your sequence to take advantage of the processor's capabilities. Whether it's SW or HW: coder, know thy compiler!

And who says data structures are exclusive to SW? Oh, you mean they aren't available in Verilog? Use a better language!

> With software, you attach a debugger, and you can step through. With VHDL, it's not that simple. So yes, I call this a different mindset. If you think like a software programmer, you'll sooner or later end up with a non-working, hard to debug prototype.

So you don't use the debugger to set breakpoints and step through complex RTL? I guess maybe not if you code too close to the edif.

Been developing FPGAs in VHDL like SW (enlightened by digital HW circuit design experience) for 20+ years now. Have fewer problems than when I tried to code netlists, doing the synthesis tool's job for it. Sure it's not _exactly_ like SW, but many, many principles of SW development are highly applicable to RTL.

> I doubt that still works for a *very* large design. On software, the OS handes a lot for you. No cache flushes, no memory barriers, etc.

I would beg to differ. Very large designs are where SW approaches make the most sense and benefit. The larger the design (and body of code), the harder it is to maintain if you don't think about it like SW.

Cache flushes are not unique to SW. The OS is just more SW. So we need to write a little more code to do that in RTL.

Can a programmer while VHDL code ? Sure. But there is a huge different between good and "it works". Every monkey can write PHP code, but writing good, maintainable code is a different story.

Yes there is a difference between SW and HW, nobody is denying that. But I've reviewed, maintained, and debugged too many RTL designs written too close to the netlist level not to recognize the benefits of SW approach to RTL.

You have to know where to pay attention to the HW (async clock boundaries are a big chunk). Then handle that close to the HW level, but encapsulate it into a few reusable entities (like system calls to the OS in SW) and then concentrate on the function, throughput and latency of the rest of the design. On a multi-person team, only one or two need to deal with the low level stuff, the rest can design at a much higher level, where the behavior of the code is critical.

Andy

 

[rickman]

On 11/9/2015 6:50 AM, igmar.palsenberg@boostermedia.com wrote:

On Sunday, November 1, 2015 at 8:27:30 AM UTC+1, rickman wrote:

I think your distinction is pointless. You said "VHDL is a description,
not a program" and I have you an example when this is not true. End of
discussion for me.

Fine. That doesn't mean you're right.

??? You don't make sense. I give you an example of VHDL that is a
program as used everyday and you reject that???

As to the "mindset", there was a software designer who wanted to code an
FPGA in VHDL and came here asking for advice. We told him about how he
needed to adjust his thinking to design hardware and not code software.
I wrote to him personally to explain why this was important and came
close to getting some consulting time with his firm. In the end his
bosses had faith that he could do a good job and so he wrote the code
himself, without any trouble.

It's a whole different thing, assuming the end result ends up on a FPGA. Software is sequenced, around datastructures. VHDL is not sequenced, and doesn't have thing software has : Lock issues, memory alignment issues, etc.

I don't think you understand VHDL. VHDL has sequential code, that is
what a process it.


> With software, you attach a debugger, and you can step through. With VHDL, it's not that simple. So yes, I call this a different mindset. If you think like a software programmer, you'll sooner or later end up with a non-working, hard to debug prototype.

Huh??? I use single stepping with VHDL at times. Normally it isn't
that useful because there is so much parallelism, things tend to jump
around as one process stops and another starts... same as software on a
processor with interrupts or multitasking.

I learned that although I was a hardware person who was able to more
easily think about the hardware I was designing as gates and register,
this is *not* required, rather you *can* write VHDL as a sequential
language as long as you understand the various processes were all in
parallel. Parallel processes are not unique to hardware.

I doubt that still works for a *very* large design. On software, the OS handes a lot for you. No cache flushes, no memory barriers, etc.

Can a programmer while VHDL code ? Sure. But there is a huge different between good and "it works". Every monkey can write PHP code, but writing good, maintainable code is a different story.

I'm not sure what you are going on about. You started by saying "VHDL
is a description, not a program." Now you seem to be splitting all
manner of hairs and calling programmers "monkeys".

Why don't we agree to disagree?

--

Rick

 

[Igmar Palsenberg]

Op dinsdag 10 november 2015 04:04:31 UTC+1 schreef Andy:

On Monday, November 9, 2015 at 5:50:51 AM UTC-6, igmar.pa...@boostermedia..com wrote:
It's a whole different thing, assuming the end result ends up on a FPGA.. Software is sequenced, around datastructures. VHDL is not sequenced, and doesn't have thing software has : Lock issues, memory alignment issues, etc..

Really? You think a modern SW compiler doesn't tweak your sequence to take advantage of the processor's capabilities. Whether it's SW or HW: coder, know thy compiler!

Sure.

> And who says data structures are exclusive to SW? Oh, you mean they aren't > available in Verilog? Use a better language!

Datastructures come at a price. In software the're cheap, in hardware the're less cheap. I need to think harder in VHDL about the structure in general.. I find myself far less limited in software (which is also a potential problem, if you ask me)

With software, you attach a debugger, and you can step through. With VHDL, it's not that simple. So yes, I call this a different mindset. If you think like a software programmer, you'll sooner or later end up with a non-working, hard to debug prototype.

So you don't use the debugger to set breakpoints and step through complex RTL? I guess maybe not if you code too close to the edif.

I did that on old Altera software. I failed at the latest version, still need to look into that. In IntelliJ, it just attach and it works (c).

> Been developing FPGAs in VHDL like SW (enlightened by digital HW circuit design experience) for 20+ years now. Have fewer problems than when I tried to code netlists, doing the synthesis tool's job for it. Sure it's not _exactly_ like SW, but many, many principles of SW development are highly applicable to RTL.

True. I have 20+ in software, not in hardware. Getting up-to-speed on VHDL again, which I last used at the university (that was 15 years ago).

I doubt that still works for a *very* large design. On software, the OS handes a lot for you. No cache flushes, no memory barriers, etc.

I would beg to differ. Very large designs are where SW approaches make the most sense and benefit. The larger the design (and body of code), the harder it is to maintain if you don't think about it like SW.

In what sense ? Cutting it up in the right modules you mean ? I especially found the VHDL variable vs signals confusing, and that fact that it looks sequential, but isn't.

> Cache flushes are not unique to SW. The OS is just more SW. So we need to write a little more code to do that in RTL.

I haven't reached that point yet

Can a programmer while VHDL code ? Sure. But there is a huge different between good and "it works". Every monkey can write PHP code, but writing good, maintainable code is a different story.

Yes there is a difference between SW and HW, nobody is denying that. But I've reviewed, maintained, and debugged too many RTL designs written too close to the netlist level not to recognize the benefits of SW approach to RTL.

You have to know where to pay attention to the HW (async clock boundaries are a big chunk). Then handle that close to the HW level, but encapsulate it into a few reusable entities (like system calls to the OS in SW) and then concentrate on the function, throughput and latency of the rest of the design. On a multi-person team, only one or two need to deal with the low level stuff, the rest can design at a much higher level, where the behavior of the code is critical.

I'm still struggling testing in VHDL. With software, I'm more confortable : Junit, gtest, mockito, pick one or combine them.
That's getting harder in the modern async works : Akka for example is message based, high-parallel.

I'm looking at vunit for VHDL at the moment, but it's still a bit confusing : Waveform in, waveform out. With software it's value in, value out.



Igmar

 

[Igmar Palsenberg]

Op dinsdag 10 november 2015 09:15:13 UTC+1 schreef rickman:

On 11/9/2015 6:50 AM, igmar.palsenberg@boostermedia.com wrote:
On Sunday, November 1, 2015 at 8:27:30 AM UTC+1, rickman wrote:

I think your distinction is pointless. You said "VHDL is a description,
not a program" and I have you an example when this is not true. End of
discussion for me.

Fine. That doesn't mean you're right.

??? You don't make sense. I give you an example of VHDL that is a
program as used everyday and you reject that???


As to the "mindset", there was a software designer who wanted to code an
FPGA in VHDL and came here asking for advice. We told him about how he
needed to adjust his thinking to design hardware and not code software..
I wrote to him personally to explain why this was important and came
close to getting some consulting time with his firm. In the end his
bosses had faith that he could do a good job and so he wrote the code
himself, without any trouble.

It's a whole different thing, assuming the end result ends up on a FPGA.. Software is sequenced, around datastructures. VHDL is not sequenced, and doesn't have thing software has : Lock issues, memory alignment issues, etc..

I don't think you understand VHDL. VHDL has sequential code, that is
what a process it.

But all of t hem run parallel. With software, it's the other way around.

With software, you attach a debugger, and you can step through. With VHDL, it's not that simple. So yes, I call this a different mindset. If you think like a software programmer, you'll sooner or later end up with a non-working, hard to debug prototype.

Huh??? I use single stepping with VHDL at times. Normally it isn't
that useful because there is so much parallelism, things tend to jump
around as one process stops and another starts... same as software on a
processor with interrupts or multitasking.

That's also getting more common in software these days. Ever tried debugging a 1M messages / second Akka application ?

I've used Altera's Max Plus II, that only had waveforms. Hooking a real simulator up with Quartus failed for me. I might try the Xilinx tools, see if I have better luck with them.

Can a programmer while VHDL code ? Sure. But there is a huge different between good and "it works". Every monkey can write PHP code, but writing good, maintainable code is a different story.

I'm not sure what you are going on about. You started by saying "VHDL
is a description, not a program." Now you seem to be splitting all
manner of hairs and calling programmers "monkeys".

I was trying to point out there is a difference between getting something to work, and actually understanding it. I failed at that


Igmar