Connect output of inverter to it's input

  • Thread starter Charles Effiong
  • Start date
C

Charles Effiong

Guest
Hi, I have this NOT gate code:

entity NOTgate is
generic (latency : time);
Port (
Data_in : in STD_LOGIC;
Data_out : out STD_LOGIC);
end NOTgate;

architecture NOTgate_arch of NOTgate is

signal data_temp : STD_LOGIC := '0';

begin
process (Data_in)
begin
data_temp <= NOT Data_in;
end process;
Data_out <= transport data_temp after latency;

end NOTgate_arch;

I now want to connect the inverter's output to its input to form a feedback loop. I Created another component as below:

entity NOTG is
generic (latency : time);
Port (
Data_in : in STD_LOGIC);
end NOTG;

architecture NOTG_arch of NOTG is
signal sig_in : STD_LOGIC := '0';
begin
sig_in <= Data_in;

NOTG0 : Entity work.NOTgate

port map(
Data_in => sig_in,
Data_out => sig_in,
);

end NOTG_arch;

This doesn't work. Where am I missing it? Thanks
 
On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote:
Le 05/04/2015 21:12, Charles Effiong a écrit :
[...]
I now want to connect the inverter's output to its input to form a feedback loop. I Created another component as below:

entity NOTG is
generic (latency : time);
Port (
Data_in : in STD_LOGIC);
end NOTG;

architecture NOTG_arch of NOTG is
signal sig_in : STD_LOGIC := '0';
begin
sig_in <= Data_in;

NOTG0 : Entity work.NOTgate
port map(
Data_in => sig_in,
Data_out => sig_in,
);
end NOTG_arch;

This doesn't work. Where am I missing it? Thanks

What exactly doesn't work ? I see several problems.
First, there shouldn't be a comma after data_out => sig_in since it's
the last association of the list. This is where you close the parenthesis..
Second, you create two drivers on sig_in, one is the entity input, the
other is the not gate output. What exactly do you think you're doing ?
Third, I don't know how the tool you're using optimizes the code but
basically, you're trying to drive an input through sig_in. This doesn't
work.
Last, are you simulating this or trying to synthesize it ? (hint :
synthesis won't work)

Nicolas
Click to expand...

Thanks @Nicolas.

"First, there shouldn't be a comma after data_out => sig_in since it's
the last association of the list"

That was a typo, I fixed that but it still doesn't work.

Basically, I want to connect the inverter's output to it's input so as to form a feed back loop. What should I do ?
 
Le 05/04/2015 21:12, Charles Effiong a ĂŠcrit :
[...]
I now want to connect the inverter's output to its input to form a feedback loop. I Created another component as below:

entity NOTG is
generic (latency : time);
Port (
Data_in : in STD_LOGIC);
end NOTG;

architecture NOTG_arch of NOTG is
signal sig_in : STD_LOGIC := '0';
begin
sig_in <= Data_in;

NOTG0 : Entity work.NOTgate
port map(
Data_in => sig_in,
Data_out => sig_in,
);
end NOTG_arch;

This doesn't work. Where am I missing it? Thanks
Click to expand...

What exactly doesn't work ? I see several problems.
First, there shouldn't be a comma after data_out => sig_in since it's
the last association of the list. This is where you close the parenthesis.
Second, you create two drivers on sig_in, one is the entity input, the
other is the not gate output. What exactly do you think you're doing ?
Third, I don't know how the tool you're using optimizes the code but
basically, you're trying to drive an input through sig_in. This doesn't
work.
Last, are you simulating this or trying to synthesize it ? (hint :
synthesis won't work)

Nicolas
 
On 05/04/15 22:11, Charles Effiong wrote:
On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote:
Le 05/04/2015 21:12, Charles Effiong a écrit :
snip
What exactly doesn't work ? I see several problems.
First, there shouldn't be a comma after data_out => sig_in since it's
the last association of the list. This is where you close the parenthesis.
Second, you create two drivers on sig_in, one is the entity input, the
other is the not gate output. What exactly do you think you're doing ?
Third, I don't know how the tool you're using optimizes the code but
basically, you're trying to drive an input through sig_in. This doesn't
work.
Last, are you simulating this or trying to synthesize it ? (hint :
synthesis won't work)

Nicolas

Thanks @Nicolas.

"First, there shouldn't be a comma after data_out => sig_in since it's
the last association of the list"

That was a typo, I fixed that but it still doesn't work.

Basically, I want to connect the inverter's output to it's input so as to form a feed back loop. What should I do ?
Click to expand...

Don't you just want

entity NOTG is
generic (latency : time);
Port (
Data_in : in STD_LOGIC);
end NOTG;

architecture NOTG_arch of NOTG is
signal sig_in : STD_LOGIC := '0';
begin

-- sig_in <= Data_in; -- <====== ??

NOTG0 : Entity work.NOTgate
generic map (latency => latency) -- <======= you forgot this
port map(
Data_in => sig_in,
Data_out => sig_in
);
end NOTG_arch;

?

I'm not sure what Data_in is for?

Alan


--
Alan Fitch
 
On Monday, April 6, 2015 at 2:01:50 AM UTC+2, Alan Fitch wrote:
On 05/04/15 22:11, Charles Effiong wrote:
On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote:
Le 05/04/2015 21:12, Charles Effiong a écrit :
snip
What exactly doesn't work ? I see several problems.
First, there shouldn't be a comma after data_out => sig_in since it's
the last association of the list. This is where you close the parenthesis.
Second, you create two drivers on sig_in, one is the entity input, the
other is the not gate output. What exactly do you think you're doing ?
Third, I don't know how the tool you're using optimizes the code but
basically, you're trying to drive an input through sig_in. This doesn't
work.
Last, are you simulating this or trying to synthesize it ? (hint :
synthesis won't work)

Nicolas

Thanks @Nicolas.

"First, there shouldn't be a comma after data_out => sig_in since it's
the last association of the list"

That was a typo, I fixed that but it still doesn't work.

Basically, I want to connect the inverter's output to it's input so as to form a feed back loop. What should I do ?


Don't you just want

entity NOTG is
generic (latency : time);
Port (
Data_in : in STD_LOGIC);
end NOTG;

architecture NOTG_arch of NOTG is
signal sig_in : STD_LOGIC := '0';
begin

-- sig_in <= Data_in; -- <====== ??

NOTG0 : Entity work.NOTgate
generic map (latency => latency) -- <======= you forgot this
port map(
Data_in => sig_in,
Data_out => sig_in
);
end NOTG_arch;

?

I'm not sure what Data_in is for?

Alan


--
Alan Fitch
Click to expand...

Thanks @Alan. I want an initial entry point into the circuit, hence "Data_in" I guess this is wrong. Also how can I connect the NOT gate output to it's input to form a loop?
 
On 06/04/15 09:36, Charles Effiong wrote:
On Monday, April 6, 2015 at 2:01:50 AM UTC+2, Alan Fitch wrote:
On 05/04/15 22:11, Charles Effiong wrote:
On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote:
Le 05/04/2015 21:12, Charles Effiong a écrit :
snip
What exactly doesn't work ? I see several problems.
First, there shouldn't be a comma after data_out => sig_in since it's
the last association of the list. This is where you close the parenthesis.
Second, you create two drivers on sig_in, one is the entity input, the
other is the not gate output. What exactly do you think you're doing ?
Third, I don't know how the tool you're using optimizes the code but
basically, you're trying to drive an input through sig_in. This doesn't
work.
Last, are you simulating this or trying to synthesize it ? (hint :
synthesis won't work)

Nicolas

Thanks @Nicolas.

"First, there shouldn't be a comma after data_out => sig_in since it's
the last association of the list"

That was a typo, I fixed that but it still doesn't work.

Basically, I want to connect the inverter's output to it's input so as to form a feed back loop. What should I do ?


Don't you just want

entity NOTG is
generic (latency : time);
Port (
Data_in : in STD_LOGIC);
end NOTG;

architecture NOTG_arch of NOTG is
signal sig_in : STD_LOGIC := '0';
begin

-- sig_in <= Data_in; -- <====== ??

NOTG0 : Entity work.NOTgate
generic map (latency => latency) -- <======= you forgot this
port map(
Data_in => sig_in,
Data_out => sig_in
);
end NOTG_arch;

?

I'm not sure what Data_in is for?

Alan


--
Alan Fitch

Thanks @Alan. I want an initial entry point into the circuit, hence "Data_in" I guess this is wrong. Also how can I connect the NOT gate output to it's input to form a loop?
Click to expand...

I don't know what you mean by "initial entry point".
I showed you how to connect the input to the output above,

regards
Alan


--
Alan Fitch
 
Le 05/04/2015 23:11, Charles Effiong a ĂŠcrit :
> That was a typo, I fixed that but it still doesn't work.

You still don't say what exactly doesn't work. That's like going to your
doctor and telling him "Doctor, I'm sick" and hoping he'll cure you with
that much information.

Nicolas
 
On Monday, April 6, 2015 at 3:29:09 PM UTC+2, Alan Fitch wrote:
On 06/04/15 09:36, Charles Effiong wrote:
On Monday, April 6, 2015 at 2:01:50 AM UTC+2, Alan Fitch wrote:
On 05/04/15 22:11, Charles Effiong wrote:
On Sunday, April 5, 2015 at 10:44:21 PM UTC+2, Nicolas Matringe wrote:
Le 05/04/2015 21:12, Charles Effiong a écrit :
snip
What exactly doesn't work ? I see several problems.
First, there shouldn't be a comma after data_out => sig_in since it's
the last association of the list. This is where you close the parenthesis.
Second, you create two drivers on sig_in, one is the entity input, the
other is the not gate output. What exactly do you think you're doing ?
Third, I don't know how the tool you're using optimizes the code but
basically, you're trying to drive an input through sig_in. This doesn't
work.
Last, are you simulating this or trying to synthesize it ? (hint :
synthesis won't work)

Nicolas

Thanks @Nicolas.

"First, there shouldn't be a comma after data_out => sig_in since it's
the last association of the list"

That was a typo, I fixed that but it still doesn't work.

Basically, I want to connect the inverter's output to it's input so as to form a feed back loop. What should I do ?


Don't you just want

entity NOTG is
generic (latency : time);
Port (
Data_in : in STD_LOGIC);
end NOTG;

architecture NOTG_arch of NOTG is
signal sig_in : STD_LOGIC := '0';
begin

-- sig_in <= Data_in; -- <====== ??

NOTG0 : Entity work.NOTgate
generic map (latency => latency) -- <======= you forgot this
port map(
Data_in => sig_in,
Data_out => sig_in
);
end NOTG_arch;

?

I'm not sure what Data_in is for?

Alan


--
Alan Fitch

Thanks @Alan. I want an initial entry point into the circuit, hence "Data_in" I guess this is wrong. Also how can I connect the NOT gate output to it's input to form a loop?


I don't know what you mean by "initial entry point".
I showed you how to connect the input to the output above,

regards
Alan


--
Alan Fitch
Click to expand...

Hi @Alan thanks, I figured it out
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top