P
Panic
Guest
I'm currently working an my master degree, and part of that
work means implementing 128/128 Rijndael on an Altera
APXA1 board. In doing this, I've ran into a problem conserning
the use of multiple archiotectures and the configurations of them.
I've tried searching the web, and reading my book (Achenden) and
the FAQ, but I haven't found a clear answer, so now I must turn to you:
I've made several "chains" of entities, where I start with one, instantiate
a couple of that one in the next entity, and then so on. What I want to do,
is configure this "chain", so that when I want to simulate my design using
one "type" of architectures (I have two architectures for each entity so
far,
"instant_rtl" and "delayed_rtl, where the latter has delays implemented), I
only need to instantiate the top level entity using the appropriate "type",
and
the choice propagates down through my design.
I have tried to use the configuration statement to do this, and it looks so
very logical and right when I write it, but when I compile and simulate
using Symphony EDA Sonata (Free Edition) it constantly uses the bottom-most
architecture in the file declaring the entity and two architectures. So what
must I do for my configuration for work as I expect?
Did I make myself clear? I fear I did't...
Anyway, I include a small code snippet. Hopefully it clarifies my problem.
----------------------------
--- Start: File ent1.vhd ---
entity ent1 is
port( ... );
end entity ent1;
architecture a1 of ent is
begin
...
end architecture a1
architecture a2 of ent is
begin
...
end architecture a2;
---- End: File ent1.vhd ----
----------------------------
--- Start: File ent2.vhd ---
entity ent2 is
port( ... );
end entity ent2;
architecture a1 of ent is
component ent1 is port(...); end component;
begin
e : ent1 port map (...);
...
end architecture a1
architecture a2 of ent2 is
component ent1 is port(...); end component;
begin
e : ent1 port map (...);
...
end architecture a2
configuration cfg of ent2 is
for a1
for e : ent1 use entity work.ent1(a1);
end for;
for a2
for e : ent1 use entity work.ent1(a2);
end for;
end configuration;
---- End: File ent2.vhd ----
----------------------------
Sincerely
- "Panic", Norwegian University of Science and Technology, Norway.
work means implementing 128/128 Rijndael on an Altera
APXA1 board. In doing this, I've ran into a problem conserning
the use of multiple archiotectures and the configurations of them.
I've tried searching the web, and reading my book (Achenden) and
the FAQ, but I haven't found a clear answer, so now I must turn to you:
I've made several "chains" of entities, where I start with one, instantiate
a couple of that one in the next entity, and then so on. What I want to do,
is configure this "chain", so that when I want to simulate my design using
one "type" of architectures (I have two architectures for each entity so
far,
"instant_rtl" and "delayed_rtl, where the latter has delays implemented), I
only need to instantiate the top level entity using the appropriate "type",
and
the choice propagates down through my design.
I have tried to use the configuration statement to do this, and it looks so
very logical and right when I write it, but when I compile and simulate
using Symphony EDA Sonata (Free Edition) it constantly uses the bottom-most
architecture in the file declaring the entity and two architectures. So what
must I do for my configuration for work as I expect?
Did I make myself clear? I fear I did't...
Anyway, I include a small code snippet. Hopefully it clarifies my problem.
----------------------------
--- Start: File ent1.vhd ---
entity ent1 is
port( ... );
end entity ent1;
architecture a1 of ent is
begin
...
end architecture a1
architecture a2 of ent is
begin
...
end architecture a2;
---- End: File ent1.vhd ----
----------------------------
--- Start: File ent2.vhd ---
entity ent2 is
port( ... );
end entity ent2;
architecture a1 of ent is
component ent1 is port(...); end component;
begin
e : ent1 port map (...);
...
end architecture a1
architecture a2 of ent2 is
component ent1 is port(...); end component;
begin
e : ent1 port map (...);
...
end architecture a2
configuration cfg of ent2 is
for a1
for e : ent1 use entity work.ent1(a1);
end for;
for a2
for e : ent1 use entity work.ent1(a2);
end for;
end configuration;
---- End: File ent2.vhd ----
----------------------------
Sincerely
- "Panic", Norwegian University of Science and Technology, Norway.