R
Rick C
Guest
This is a good example of how rusty I am. I like to use variables where I can because it localizes the scope. So I have an accumulator that is incremented in a clocked process. Then I want to use a portion of the result depending on a control, much like a mux, but no register is required, just combinatorial logic.
process (rst, clk) is
variable...
begin
if (rst)
... initialization stuff
elsif (rising_edge(Clk)) then
accum := (accum + input) mod modulus;
end if;
if (condition) then
output <= accum / 2;
else
output <= accum;
end if;
end process;
I want to say that while the non-clocked IF will be synthesize as combinatorial logic and not a register. In the simulation it will look like a register because the value will change on the rising edge of the clock because accum is a variable and so updated right away. Accum will be registered, but output will not be.
Or will accum not be registered and output registered??? I guess I could try some synthesis to see what happens.
I\'m pretty sure I\'ve done this sort of thing before and it works fine.
--
Rick C.
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process (rst, clk) is
variable...
begin
if (rst)
... initialization stuff
elsif (rising_edge(Clk)) then
accum := (accum + input) mod modulus;
end if;
if (condition) then
output <= accum / 2;
else
output <= accum;
end if;
end process;
I want to say that while the non-clocked IF will be synthesize as combinatorial logic and not a register. In the simulation it will look like a register because the value will change on the rising edge of the clock because accum is a variable and so updated right away. Accum will be registered, but output will not be.
Or will accum not be registered and output registered??? I guess I could try some synthesis to see what happens.
I\'m pretty sure I\'ve done this sort of thing before and it works fine.
--
Rick C.
- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209